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N32G452CBL7

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by Ray

Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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N32G452CBL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

N32G452CBL7 from Nations Technologies Inc, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup power supply for RTC/backup domain when VDD is absent (1.8 V-3.6 V).
2 PC13-TAMPER-RTC bidirectional GPIO PC13, alternate functions TAMPER input and RTC output. Backup-domain pin, limited drive.
3 PC14-OSC32_IN bidirectional GPIO PC14 or low-speed 32.768 kHz crystal oscillator input (LSE).
4 PC15-OSC32_OUT bidirectional GPIO PC15 or low-speed 32.768 kHz crystal oscillator output (LSE).
5 PD0-OSC_IN bidirectional High-speed external crystal input (HSE, 4-32 MHz) or GPIO PD0 in LQFP48 remapped configuration.
6 PD1-OSC_OUT bidirectional High-speed external crystal output (HSE) or GPIO PD1 in LQFP48 remapped configuration.
7 NRST bidirectional Bidirectional device reset input (active low) with internal pull-up; also driven low by internal reset sources.
8 VSSA power_in Analog ground reference for ADC/DAC and analog blocks.
9 VDDA power_in Analog supply for ADC/DAC and analog blocks (1.8-3.6 V). Also serves as ADC reference on LQFP48 (no dedicated VREF+ pin).
10 PA0-WKUP bidirectional GPIO PA0 with WKUP wake-up input; alt functions USART2_CTS, ADC1_IN1, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, SPI3_MISO.
11 PA1 bidirectional GPIO PA1; alt USART2_RTS, ADC1_IN2, TIM2_CH2, TIM5_CH2, SPI3_MOSI/I2S3_SD.
12 PA2 bidirectional GPIO PA2; alt USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3.
13 PA3 bidirectional GPIO PA3; alt USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4.
14 PA4 bidirectional GPIO PA4; alt SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, I2C2_SCL.
15 PA5 bidirectional GPIO PA5; alt SPI1_SCK, DAC_OUT2, ADC2_IN2, I2C2_SDA.
16 PA6 bidirectional GPIO PA6; alt SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, TIM1_BKIN, QSPI_IO0.
17 PA7 bidirectional GPIO PA7; alt SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, TIM1_CH1N, QSPI_IO1.
18 PB0 bidirectional GPIO PB0; alt TIM3_CH3, TIM1_CH2N, TIM8_CH2N, UART6_TX.
19 PB1 bidirectional GPIO PB1; alt TIM3_CH4, ADC2_IN3, TIM1_CH3N, TIM8_CH3N, UART6_RX.
20 PB2-BOOT1 bidirectional GPIO PB2 / BOOT1 boot-mode select input; alt ADC2_IN13, UART4_TX, SPI1_NSS.
21 PB10 bidirectional GPIO PB10; alt I2C2_SCL, USART3_TX, TIM2_CH3, XFMC_D11.
22 PB11 bidirectional GPIO PB11; alt I2C2_SDA, USART3_RX, TIM2_CH4, XFMC_D12.
23 VSS_1 power_in Digital ground.
24 VDD_1 power_in Digital supply, 1.8-3.6 V.
25 PB12 bidirectional GPIO PB12; alt SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX.
26 PB13 bidirectional GPIO PB13; alt SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, UART5_TX.
27 PB14 bidirectional GPIO PB14; alt SPI2_MISO, TIM1_CH2N, USART3_RTS, UART5_RX.
28 PB15 bidirectional GPIO PB15; alt SPI2_MOSI/I2S2_SD, TIM1_CH3N.
29 PA8 bidirectional GPIO PA8; alt USART1_CK, TIM1_CH1, MCO clock output, XFMC_NOE.
30 PA9 bidirectional GPIO PA9; alt USART1_TX, TIM1_CH2, I2C4_SCL.
31 PA10 bidirectional GPIO PA10; alt USART1_RX, TIM1_CH3, I2C4_SDA, XFMC_MWE.
32 PA11 bidirectional GPIO PA11; alt USART1_CTS, USBDM (USB D-), CAN1_RX, TIM1_CH4.
33 PA12 bidirectional GPIO PA12; alt USART1_RTS, USBDP (USB D+), CAN1_TX, TIM1_ETR.
34 PA13 bidirectional GPIO PA13 / JTMS-SWDIO debug pin; default after reset is JTMS-SWDIO with internal pull-up. Alt UART4_TX.
35 VSS_2 power_in Digital ground.
36 VDD_2 power_in Digital supply, 1.8-3.6 V.
37 PA14 bidirectional GPIO PA14 / JTCK-SWCLK debug clock pin; default after reset is JTCK-SWCLK with internal pull-down. Alt UART4_RX.
38 PA15 bidirectional GPIO PA15 / JTDI JTAG data-in; alt SPI3_NSS/I2S3_WS, SPI1_NSS, USART2_CTS, TIM2_CH1_ETR.
39 PB3 bidirectional GPIO PB3 / JTDO-TRACESWO JTAG data-out/trace; alt SPI1_SCK, SPI3_SCK/I2S3_CK, TIM2_CH2, USART1 remap functions.
40 PB4 bidirectional GPIO PB4 / NJTRST JTAG reset; alt SPI1_MISO, SPI3_MISO, TIM3_CH1 remap.
41 PB5 bidirectional GPIO PB5; alt I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, TIM3_CH2, CAN2_RX remap.
42 PB6 bidirectional GPIO PB6; alt I2C1_SCL, USART1_TX (remap), TIM4_CH1, CAN2_TX remap.
43 PB7 bidirectional GPIO PB7; alt I2C1_SDA, USART1_RX (remap), TIM4_CH2, XFMC_NADV.
44 BOOT0 input Boot-mode select input sampled at reset together with BOOT1 (PB2) to choose boot source (Flash / System memory / SRAM).
45 PB8 bidirectional GPIO PB8; alt I2C1_SCL (remap), TIM4_CH3, CAN1_RX remap, SDIO_D4.
46 PB9 bidirectional GPIO PB9; alt I2C1_SDA (remap), TIM4_CH4, CAN1_TX remap, SDIO_D5.
47 VSS_3 power_in Digital ground.
48 VDD_3 power_in Digital supply, 1.8-3.6 V.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-48(7x7)
Category MCU
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • N32G452CBL7
  • N32G452CCL7
  • N32G452RBL7
  • N32G452RCL7
  • N32G452MBL7
  • N32G452MCL7
  • N32G452MEL7
  • N32G452VBL7
  • N32G452VCL7
  • N32G452VEL7
  • N32G452QCL7
  • N32G452QEL7

CAD (KiCad official)

  • Symbol: N32G452CBL7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (96 pp, sha256 64263c0a0ef9dd52, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF