MSP430I2040TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A0.0+	input	SD24 positive analog input channel A0.0 (differential PGA input). Short unused analog input pairs together and connect to analog ground (AVSS).
2	A0.0-	input	SD24 negative analog input channel A0.0 (differential PGA input).
3	A1.0+	input	SD24 positive analog input channel A1.0 (differential PGA input).
4	A1.0-	input	SD24 negative analog input channel A1.0 (differential PGA input).
5	A2.0+	input	SD24 positive analog input channel A2.0 (differential PGA input).
6	A2.0-	input	SD24 negative analog input channel A2.0 (differential PGA input).
7	A3.0+	input	SD24 positive analog input channel A3.0 (differential PGA input).
8	A3.0-	input	SD24 negative analog input channel A3.0 (differential PGA input).
9	VREF	passive	SD24 external reference voltage input. When SD24 operates with internal reference (SD24REFS=1), leave VREF unloaded except for the recommended C_VREF decoupling capacitor to AVSS.
10	AVSS	power_in	Analog supply voltage negative terminal (analog ground).
11	ROSC	passive	External resistor pin for the DCO. In external-resistor mode, connect the recommended resistor between ROSC and AVSS; in internal-resistor mode, tie ROSC to AVSS.
12	DVSS	power_in	Digital supply voltage negative terminal (digital ground). TI recommends bonding the RHB package thermal pad to DVSS.
13	VCC	power_in	Analog and digital supply voltage positive terminal. Operating range 2.2 V to 3.6 V.
14	VCORE	passive	Regulated 1.8 V core supply output (internal use only, no external current loading). Connect only the recommended C_VCORE decoupling capacitor.
15	RST/NMI/SBWTDIO	bidirectional	Reset or non-maskable interrupt input; also Spy-Bi-Wire test data input/output for device programming and debug. Terminate with a 47 kohm pullup to VCC and 10 nF (or 2.2 nF) pulldown.
16	TEST/SBWTCK	input	Selects JTAG test mode on pins P1.0-P1.3 and serves as the Spy-Bi-Wire test clock input for device programming and debug. Has an internal pulldown.
17	P1.0/UCA0STE/MCLK/TCK	bidirectional	GPIO P1.0; alternate functions eUSCI_A0 SPI slave-transmit-enable, MCLK output, and JTAG test clock (TCK) for programming/debug.
18	P1.1/UCA0CLK/SMCLK/TMS	bidirectional	GPIO P1.1; alternate functions eUSCI_A0 clock, SMCLK output, and JTAG test-mode select (TMS).
19	P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK	bidirectional	GPIO P1.2; eUSCI_A0 UART RXD or SPI slave-out/master-in, ACLK output, and JTAG TDI / TCLK for programming/debug.
20	P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI	bidirectional	GPIO P1.3; eUSCI_A0 UART TXD or SPI slave-in/master-out, Timer_A0 external clock (TACLK), and JTAG TDO / TDI programming pin.
21	P1.4/UCB0STE/TA0.0	bidirectional	GPIO P1.4; eUSCI_B0 SPI slave-transmit-enable and Timer_A0 CCR0 capture (CCI0A) / compare (Out0).
22	P1.5/UCB0CLK/TA0.1	bidirectional	GPIO P1.5; eUSCI_B0 clock and Timer_A0 CCR1 capture (CCI1A) / compare (Out1).
23	P1.6/UCB0SCL/UCB0SOMI/TA0.2	bidirectional	GPIO P1.6; eUSCI_B0 I2C clock (SCL) or SPI slave-out/master-in, and Timer_A0 CCR2 capture (CCI2A) / compare (Out2).
24	P1.7/UCB0SDA/UCB0SIMO/TA1CLK	bidirectional	GPIO P1.7; eUSCI_B0 I2C data (SDA) or SPI slave-in/master-out, and Timer_A1 external clock (TACLK).
25	P2.0/TA1.0/CLKIN	bidirectional	GPIO P2.0; Timer_A1 CCR0 capture (CCI0A) / compare (Out0); DCO bypass clock input (CLKIN).
26	P2.1/TA1.1	bidirectional	GPIO P2.1; Timer_A1 CCR1 capture (CCI1A) / compare (Out1).
27	P2.2/TA1.2	bidirectional	GPIO P2.2; Timer_A1 CCR2 capture (CCI2A) / compare (Out2).
28	P2.3/VMONIN	bidirectional	GPIO P2.3; also voltage monitor analog input (VMONIN) for the supply voltage monitor.
29	P2.4/TA1.0	bidirectional	GPIO P2.4; Timer_A1 CCR0 capture (CCI0B) / compare (Out0). Available only on the RHB package.
30	P2.5/TA0.0	bidirectional	GPIO P2.5; Timer_A0 CCR0 capture (CCI0B) / compare (Out0). Available only on the RHB package.
31	P2.6/TA0.1	bidirectional	GPIO P2.6; Timer_A0 CCR1 compare (Out1). Available only on the RHB package.
32	P2.7/TA0.2	bidirectional	GPIO P2.7; Timer_A0 CCR2 compare (Out2). Available only on the RHB package.
33	EP	power_in	Exposed thermal pad on the underside of the RHB VQFN package. TI recommends connecting the thermal pad to DVSS.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	MCU
Pins	33

Ordering variants

Same part, different packaging or reel option.

MSP430I2040TRHBR
MSP430I2040TRHBT
MSP430I2040TRHBRTPW
MSP430I2040TRHBRTPWR

CAD (KiCad official)

Symbol: MSP430I2040TRHBR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (81 pp, sha256 e9594c89ece53373, retrieved 2026-08-17, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF