MSP430FR2422IPW16 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1.1/UCB0CLK/ACLK/A1/VREF+	bidirectional	General-purpose I/O P1.1 (reset default). Muxed with eUSCI_B0 SPI clock (UCB0CLK), ACLK output, ADC analog input A1, and positive reference voltage output VREF+. LVCMOS/Analog buffer, powered from DVCC (1.8-3.6V).
2	P1.0/UCB0STE/A0/Veref+	bidirectional	General-purpose I/O P1.0 (reset default). Muxed with eUSCI_B0 SPI slave-transmit-enable (UCB0STE), ADC analog input A0, and ADC external positive reference input Veref+. LVCMOS/Analog buffer, powered from DVCC.
3	TEST/SBWTCK	input	Test-mode select for JTAG (TEST) and Spy-Bi-Wire input clock (SBWTCK). Selects between JTAG shared function on P1.4-P1.7 and normal digital I/O. Has an internal pulldown always enabled; leave open if unused. LVCMOS input, DVCC-referenced.
4	RST/NMI/SBWTDIO	bidirectional	Active-low reset input (RST), non-maskable interrupt input (NMI), and Spy-Bi-Wire data I/O (SBWTDIO). Recommended termination: 47-kΩ pullup to DVCC with a ≤1.1-nF pulldown capacitor when using Spy-Bi-Wire debug tooling. LVCMOS, DVCC-referenced.
5	DVCC	power_in	Digital + analog core/IO supply. Recommended operating range 1.8V to 3.6V (minimum limited by SVS level). Decouple with 4.7-10µF bulk plus 100nF ceramic close to the pin; supply slew must remain below 0.2V/µs to avoid BOR.
6	DVSS	power_in	Digital and analog ground return (0V reference for DVCC). All device signal voltages are referenced to DVSS.
7	P2.1/UCA0RXD/UCA0SOMI/XIN	bidirectional	General-purpose I/O P2.1 (reset default). Muxed with eUSCI_A0 UART receive (UCA0RXD) or SPI slave-out/master-in (UCA0SOMI) via the USCIARMP remap, and with the LFXT crystal oscillator input XIN. LVCMOS buffer, DVCC-referenced.
8	P2.0/UCA0TXD/UCA0SIMO/XOUT	bidirectional	General-purpose I/O P2.0 (reset default). Muxed with eUSCI_A0 UART transmit (UCA0TXD) or SPI slave-in/master-out (UCA0SIMO) via the USCIARMP remap, and with the LFXT crystal oscillator output XOUT. LVCMOS buffer, DVCC-referenced.
9	P2.2/TA1.1/A4	bidirectional	General-purpose I/O P2.2 (reset default). Muxed with Timer_A1 CCR1 capture/compare (TA1.1) and ADC analog input A4. LVCMOS/Analog buffer, DVCC-referenced.
10	P1.7/UCA0STE/TDO	bidirectional	General-purpose I/O P1.7 (reset default). Muxed with eUSCI_A0 SPI slave-transmit-enable (UCA0STE) and JTAG test data output (TDO). LVCMOS buffer, DVCC-referenced.
11	P1.6/UCA0CLK/TA0CLK/TDI/TCLK	bidirectional	General-purpose I/O P1.6 (reset default). Muxed with eUSCI_A0 SPI clock (UCA0CLK), Timer_A0 external clock (TA0CLK), and JTAG test data input / test clock (TDI/TCLK). LVCMOS buffer, DVCC-referenced.
12	P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS	bidirectional	General-purpose I/O P1.5 (reset default). Muxed with eUSCI_A0 UART receive (UCA0RXD) or SPI slave-out/master-in (UCA0SOMI) via the USCIARMP remap, Timer_A0 CCR2 capture/compare (TA0.2), and JTAG test mode select (TMS). LVCMOS buffer, DVCC-referenced.
13	P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK	bidirectional	General-purpose I/O P1.4 (reset default). Muxed with eUSCI_A0 UART transmit (UCA0TXD) or SPI slave-in/master-out (UCA0SIMO) via the USCIARMP remap, Timer_A0 CCR1 capture/compare (TA0.1), and JTAG test clock (TCK). LVCMOS buffer, DVCC-referenced.
14	DNC	unconnected	Do Not Connect. Leave this pin electrically unconnected on the board.
15	P1.3/UCB0SOMI/UCB0SCL/MCLK/A3	bidirectional	General-purpose I/O P1.3 (reset default). Muxed with eUSCI_B0 SPI slave-out/master-in (UCB0SOMI) or I2C clock (UCB0SCL), MCLK output, and ADC analog input A3. LVCMOS/Analog buffer, DVCC-referenced.
16	P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-	bidirectional	General-purpose I/O P1.2 (reset default). Muxed with eUSCI_B0 SPI slave-in/master-out (UCB0SIMO) or I2C data (UCB0SDA), SMCLK output, ADC analog input A2, and ADC external negative reference input Veref-. LVCMOS/Analog buffer, DVCC-referenced.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Embedded Processors & Controllers
Pins	16

Ordering variants

Same part, different packaging or reel option.

MSP430FR2422IPW16
MSP430FR2422IPW16R
MSP430FR2422IPW16IRHL
MSP430FR2422IPW16IRHLR
MSP430FR2422IPW16IRHLT

CAD (KiCad official)

Symbol: MSP430FR2422IPW16
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 4854cd8a5843413c, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF