MS51FC0AE from Nuvoton Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P0.5/ADC_CH4/PWM0_CH2/PWM2_CH0/UART3_TXD/T0/IC6	bidirectional	Port 0 bit 5. Multiplexed with ADC input channel 4, PWM0 channel 2, PWM2 channel 0, UART3 TXD, Timer/Counter 0 external count input (T0), and Timer2 input capture channel 6.
2	P0.6/ADC_CH3/UART0_TXD	bidirectional	Port 0 bit 6. Multiplexed with ADC input channel 3 and UART0 transmit data output.
3	P0.7/ADC_CH2/UART0_RXD	bidirectional	Port 0 bit 7. Multiplexed with ADC input channel 2 and UART0 receive data input. UART0_TXD and UART0_RXD are software-exchangeable via AUXR1.2.
4	P2.0/nRESET	input	Combined Port 2 bit 0 (input-only when CONFIG0.2 RPD is programmed to 0) and Schmitt-trigger active-low hardware reset. nRESET has an internal pull-up; a low level on this pin resets the device.
5	P3.0/ADC_CH1/SPI0_MOSI/UART2_TXD/INT0/OSCIN/SC0_CLK	bidirectional	Port 3 bit 0. Multiplexed with ADC channel 1, SPI0 MOSI, UART2 TXD, external interrupt 0 (INT0), external clock input (OSCIN when EXTEN[1:0]=11b), and Smart Card 0 clock (SC0_CLK).
6	P1.7/ADC_CH0/SPI0_CLK/UART2_RXD/INT1/SC0_DAT	bidirectional	Port 1 bit 7. Multiplexed with ADC channel 0, SPI0 clock, UART2 RXD, external interrupt 1 (INT1), and Smart Card 0 data pin.
7	VSS	power_in	Ground potential (0 V) reference for digital and analog supplies.
8	P1.6/I2C0_SDA/UART1_TXD/ICE_DAT	bidirectional	Port 1 bit 6. Multiplexed with I2C0 data line (SDA), UART1 transmit data output, and ICE/ICP debug data pin.
9	VDD	power_in	Positive supply voltage for chip operation. Recommended operating range per Section 8.1 general operating conditions.
10	P1.5/PWM0_CH5/PWM3_CH1/SPI0_SS/UART3_TXD/SC1_CLK/IC7	bidirectional	Port 1 bit 5. Multiplexed with PWM0 channel 5, PWM3 channel 1, SPI0 slave-select, UART3 TXD, Smart Card 1 clock, and Timer2 input capture channel 7.
11	P1.4/ADC_CH14/PWM0_CH1/PWM1_CH1/I2C0_SDA/PWM0_BRAKE	bidirectional	Port 1 bit 4. Multiplexed with ADC channel 14, PWM0/PWM1 channel 1, I2C0 data (alternate mapping via I2CPX), and PWM0 fault-brake input.
12	P1.3/ADC_CH13/I2C0_SCL/STADC	bidirectional	Port 1 bit 3. Multiplexed with ADC channel 13, I2C0 clock, and external ADC start trigger (STADC).
13	P1.2/PWM0_CH0/PWM1_CH0/UART3_TXD/SC1_CLK/IC0	bidirectional	Port 1 bit 2. Multiplexed with PWM0/PWM1 channel 0, UART3 TXD, Smart Card 1 clock, and Timer2 input capture channel 0.
14	P1.1/ADC_CH7/PWM0_CH1/PWM1_CH1/UART3_RXD/SC1_DAT/CLKO/IC1	bidirectional	Port 1 bit 1. Multiplexed with ADC channel 7, PWM0/PWM1 channel 1, UART3 RXD, Smart Card 1 data, system clock output (CLKO), and Timer2 input capture channel 1.
15	P1.0/PWM0_CH2/PWM2_CH0/SPI0_CLK/UART1_TXD/IC2	bidirectional	Port 1 bit 0. Multiplexed with PWM0 channel 2, PWM2 channel 0, SPI0 clock, UART1 TXD (note: table also labels this UART1_RX; verify with device errata), and Timer2 input capture channel 2.
16	P0.0/PWM0_CH3/PWM2_CH1/SPI0_MOSI/UART1_RXD/XT1_IN/OSCIN/T1/IC3	bidirectional	Port 0 bit 0. Multiplexed with PWM0 channel 3, PWM2 channel 1, SPI0 MOSI, UART1 RXD, external 4-24 MHz crystal input (XT1_IN / HXTIN), external clock input (OSCIN when EXTEN[1:0]=10b), Timer/Counter 1 external input (T1), and Timer2 input capture channel 3.
17	P0.1/PWM0_CH4/PWM3_CH0/SPI0_MISO/XT1_OUT/HXTOUT/IC4	bidirectional	Port 0 bit 1. Multiplexed with PWM0 channel 4, PWM3 channel 0, SPI0 MISO, external 4-24 MHz crystal output (XT1_OUT / HXTOUT), and Timer2 input capture channel 4.
18	P0.2/I2C0_SCL/UART1_RXD/ICE_CLK	bidirectional	Port 0 bit 2. Multiplexed with I2C0 clock, UART1 RXD, and ICE/ICP debug clock input.
19	P0.3/ADC_CH6/PWM0_CH5/PWM3_CH1/UART2_TXD/SC0_CLK/IC5	bidirectional	Port 0 bit 3. Multiplexed with ADC channel 6, PWM0 channel 5, PWM3 channel 1, UART2 TXD, Smart Card 0 clock, and Timer2 input capture channel 5.
20	P0.4/ADC_CH5/PWM0_CH3/PWM2_CH1/UART2_RXD/SC0_DAT/STADC/IC3	bidirectional	Port 0 bit 4. Multiplexed with ADC channel 5, PWM0 channel 3, PWM2 channel 1, UART2 RXD, Smart Card 0 data, external ADC start trigger (STADC), and Timer2 input capture channel 3.

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	TSSOP-20
Category	MCU
Pins	20

Ordering variants

Same part, different packaging or reel option.

MS51FC0AE
MS51XC0BE
MS51EC0AE
MS51PC0AE
MS51TC0AE

CAD (KiCad official)

Symbol: MS51FC0AE
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`ms51fc0ae.step`	267 KB	You want the bare part, or you mark your own boards.
`ms51fc0ae-etched.step`	2.4 MB	You want the part with `MS51FC0AE` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 617 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (80 pp, sha256 3ef54b54d90b3470, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF