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Pinout
Key specifications
CAD (KiCad official)
Provenance

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MS1023

Hangzhou Ruimeng Tech · LVDS ICs · SSOP-28-208mil

MS1023 from Hangzhou Ruimeng Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SYNC1	input	LVTTL sync input, ORed with SYNC2. Holding either SYNC input high for >6 TCLK periods triggers transmission of at least 1026 SYNC-pattern symbols on the LVDS output to help the receiver lock.
2	SYNC2	input	LVTTL sync input, ORed with SYNC1. Holding either SYNC input high for >6 TCLK periods triggers transmission of at least 1026 SYNC-pattern symbols.
3	DIN0	input	Parallel LVTTL data input bit 0. Latched into the serializer on the TCLK edge selected by TCLK_R/F.
4	DIN1	input	Parallel LVTTL data input bit 1.
5	DIN2	input	Parallel LVTTL data input bit 2.
6	DIN3	input	Parallel LVTTL data input bit 3.
7	DIN4	input	Parallel LVTTL data input bit 4.
8	DIN5	input	Parallel LVTTL data input bit 5.
9	DIN6	input	Parallel LVTTL data input bit 6.
10	DIN7	input	Parallel LVTTL data input bit 7.
11	DIN8	input	Parallel LVTTL data input bit 8.
12	DIN9	input	Parallel LVTTL data input bit 9 (MSB).
13	TCLK_R/F	input	LVTTL edge-select input. Low = ignore TCLK falling-edge data (latch on rising edge); High = ignore TCLK rising-edge data (latch on falling edge).
14	TCLK	input	LVTTL reference clock input, 10 MHz to 80 MHz. Latches the parallel input data and provides the PLL reference frequency.
15	DGND	power_in	Digital circuit ground.
16	DGND	power_in	Digital circuit ground.
17	AVCC	power_in	Analog circuit supply for the PLL and analog blocks. Vcc = 3.0 V to 3.6 V (3.3 V typical).
18	AGND	power_in	Analog circuit ground (for PLL and analog blocks).
19	DEN	input	LVTTL LVDS output-enable input. Low forces the LVDS serial output (DO+/DO-) into high impedance; High enables serial data transmission.
20	AGND	power_in	Analog circuit ground (for PLL and analog blocks).
21	DO-	output	LVDS differential serial output, negative side.
22	DO+	output	LVDS differential serial output, positive side.
23	AGND	power_in	Analog circuit ground (for PLL and analog blocks).
24	PWRDN	input	Active-low LVTTL power-down input. Low turns off the PLL, forces the LVDS output to high impedance, and puts the serializer into a µA-level sleep mode. Drive high to resume; a re-initialization (1026 TCLK periods) is required to re-lock.
25	AGND	power_in	Analog circuit ground (for PLL and analog blocks).
26	AVCC	power_in	Analog circuit supply for the PLL and analog blocks. Vcc = 3.0 V to 3.6 V.
27	DVCC	power_in	Digital circuit supply. Vcc = 3.0 V to 3.6 V (3.3 V typical).
28	DVCC	power_in	Digital circuit supply. Vcc = 3.0 V to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	Hangzhou Ruimeng Tech
Package	SSOP-28-208mil
Category	Interface
Pins	28

CAD (KiCad official)

Symbol: MS1023
Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
3D model: SSOP-28-208mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Hangzhou Ruimeng Tech datasheet (None pp, sha256 a2a820963051c0eb, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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