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MP4473GL-Z

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by Ray

Monolithic Power Systems DC-DC Converters, QFN-20(3x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentpower management (pmic)mp4473gl-z
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Contents

README

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MP4473GL-Z

Monolithic Power Systems · DC-DC Converters · QFN-20(3x4)

MP4473GL-Z from Monolithic Power Systems, in a QFN-20(3x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground. Quiet reference for the internal analog circuitry; connect to the system ground plane with a low-impedance path.
2 FREQ input Frequency set (CCM). A resistor from FREQ to GND (with VIN sensing) programs the on-time and thus the switching frequency (200kHz-1MHz). Decouple with a 1nF capacitor.
3 FB input Feedback input. Tap of the external resistor divider from VOUT to GND that sets the output voltage; the internal reference is 0.8V (1% tolerance).
4 SS bidirectional Soft-start. An external capacitor programs the soft-start ramp. When EN is HIGH, an 8.5µA internal current source charges the cap and SS ramps 0→VFB; when EN goes LOW, the cap is discharged.
5 EN input Enable input. EN=1 enables the converter. For automatic start-up, tie EN to IN through a 100kΩ resistor. Contains an internal 1MΩ pull-down.
6 PGOOD output Power-good open-drain output. Goes HIGH once VFB ≥ 90% of the nominal reference; there is roughly a 700µs delay from FB reaching 90% to PGOOD asserting HIGH. Requires an external pull-up resistor.
7 BST passive Bootstrap. Connect a 0.1µF-1µF capacitor from BST to SW to form a floating supply for the high-side MOSFET gate driver.
8 IN power_in Supply voltage input, 4.5V-36V operating range. Pins 8, 19, 21, 22, 23 are all tied to IN internally; decouple with CIN close to the device using wide traces and multiple vias.
9 SW output Switch node output. Pins 9, 10, 17, 18, 24, 25 are all tied to SW; connect through the external inductor to VOUT. Use wide traces and multiple vias.
10 SW output Switch node output (see pin 9).
11 PGND power_in Power ground. Return for the low-side power MOSFET and reference for the regulated output. Pins 11-16 all tie to PGND; careful layout is required.
12 PGND power_in Power ground (see pin 11).
13 PGND power_in Power ground (see pin 11).
14 PGND power_in Power ground (see pin 11).
15 PGND power_in Power ground (see pin 11).
16 PGND power_in Power ground (see pin 11).
17 SW output Switch node output (see pin 9).
18 SW output Switch node output (see pin 9).
19 IN power_in Supply voltage input (see pin 8).
20 VCC power_out Internal 5V LDO bias supply output. Decouple with a 1µF capacitor placed as close to the pin as possible; do not use to power external loads.
21 IN power_in Supply voltage input, exposed pad (see pin 8).
22 IN power_in Supply voltage input, exposed pad (see pin 8).
23 IN power_in Supply voltage input, exposed pad (see pin 8).
24 SW output Switch node output, exposed pad (see pin 9).
25 SW output Switch node output, exposed pad (see pin 9).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package QFN-20(3x4)
Category Power Management (PMIC)
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • MP4473GL-Z

CAD (KiCad official)

  • Symbol: MP4473GL-Z
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm
  • 3D model: QFN-20(3x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (None pp, sha256 f63834b9a4b2c9e3, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF