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MP3364GR-Z

Monolithic Power Systems · LED Drivers · QFN-24(4x4)

MP3364GR-Z from Monolithic Power Systems, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIM input PWM signal input pin for brightness control. Internally pulled low; recommended PWM frequency 100Hz to 20kHz. VDIM_LO = 0.4V (max, falling), VDIM_HI = 1.2V (min, rising).
2 MIX/AD input Dimming mode setting pin with 18μA current-source output. Voltage set by external resistor: <0.3V = mixed dimming, 0.5V-0.8V = PWM dimming, 1.0V-1.3V = analog dimming; float to use internal MODE register.
3 FREQ/SYNC bidirectional Switching frequency setting and external SYNC pin. Resistor to GND sets fSW (fSW(kHz)=22000/R(kΩ)), or drive with an external clock to synchronize. Float to use internal FSW1:0 register. VFREQ ≈ 0.6V.
4 EN input IC enable pin. Pull high to enable (VEN_ON = 1.2V min rising), pull low to shut down (VEN_OFF = 0.4V max falling). 1MΩ internal pull-down resistor.
5 SCL/PSE bidirectional I2C interface clock input. Alternatively, tie SCL/PSE together with SDA/PSE and bias between 0.75V and 1V to enable the phase-shift PWM dimming function. Tie to GND if phase shift is not used.
6 SDA/PSE bidirectional I2C interface data input. Alternatively, tie SDA/PSE together with SCL/PSE and bias between 0.75V and 1V to enable the phase-shift PWM dimming function. Tie to GND if phase shift is not used.
7 COMP passive Loop compensation pin for the boost converter error amplifier. Connect an RC compensation network from COMP to AGND. GCOMP ≈ 100μA/V; source/sink limits 90μA/30μA.
8 FF output Fault flag output. Open-drain; high (via external pull-up) during normal operation and pulled low if a fault occurs. VOL = 0.4V max at ILOAD = 3mA.
9 ISET passive LED full-scale current setting. Tie a resistor from ISET to GND to set per-string LED current: ILED(mA) = 1245/R_ISET(kΩ). VISET ≈ 1.2V; RISET = 24.9kΩ yields ILED = 50mA.
10 AGND power_in Analog ground reference. All logic signals must be referenced to AGND. Externally connect to PGND and to the exposed pad.
11 AGND power_in Analog ground reference. All logic signals must be referenced to AGND. Externally connect to PGND and to the exposed pad.
12 AGND power_in Analog ground reference. All logic signals must be referenced to AGND. Externally connect to PGND and to the exposed pad.
13 LED4 input LED string 4 current input (cathode). Sinks up to 150mA of regulated string current. Headroom VHD ≈ 350mV at 20mA, ≈850mV at 100mA. Absolute max 50V. Tie to GND if unused (auto-detected).
14 LED3 input LED string 3 current input (cathode). Sinks up to 150mA of regulated string current. Headroom VHD ≈ 350mV at 20mA, ≈850mV at 100mA. Absolute max 50V.
15 LED2 input LED string 2 current input (cathode). Sinks up to 150mA of regulated string current. Headroom VHD ≈ 350mV at 20mA, ≈850mV at 100mA. Absolute max 50V.
16 LED1 input LED string 1 current input (cathode). Sinks up to 150mA of regulated string current. Headroom VHD ≈ 350mV at 20mA, ≈850mV at 100mA. Absolute max 50V.
17 PGND power_in Step-up converter power ground; source of the internal low-side MOSFET. Route away from logic and connect externally to AGND with a short, low-inductance path.
18 SW power_out Drain of the internal low-side N-channel MOSFET switch (RDS(ON) ≈ 100mΩ). Connect the boost inductor here. Absolute max 50V (transient -1.0V <100ns).
19 OVP input Over-voltage protection sense input. Connect a resistor divider from VOUT to OVP to GND to set the OVP threshold; internal VOVP ≈ 2V (nominal), 200mV hysteresis, 100mV UVLO threshold for VOUT-short detection.
20 STH passive Short-LED protection threshold set pin, 18μA current source. Connect a resistor to GND: V_STH = 0.18 × R_STH(kΩ); actual threshold is 10 × V_STH. Float to use internal TH_S1:0 register (2.5V/5V/7.5V/10V).
21 ADR input I2C slave address select. 18μA pull-up: floating → 0x38, <0.4V → 0x3A, 0.4V-1.4V → 0x39. Program via resistor to GND.
22 VCC power_out Internal 5V LDO output that powers the internal logic and gate driver. Bypass to AGND with a ceramic capacitor (e.g., 1μF) placed close to the pin. Valid for 6V < VIN < 24V, 0-10mA load.
23 SD output Gate drive for an optional external disconnect P-channel MOSFET between VIN and VOUT path. Turns off the external PMOS when a fault occurs (VIN − VSD ≈ 6V clamp; 60μA pull-down current). Float if unused.
24 VIN power_in Power supply input to the IC. Operating range 3.5V to 36V (absolute max 42V). UVLO rising threshold ≈ 3.1V with 100mV hysteresis. Bypass to PGND with a low-ESR ceramic (e.g., 10μF).
EP AGND power_in Exposed thermal pad on the bottom of the QFN. Connect to AGND with multiple vias for electrical reference and heat sinking (θJA = 42°C/W on JESD51-7 4-layer PCB).

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package QFN-24(4x4)
Category LED Drivers
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • MP3364GR-Z

CAD (KiCad official)

  • Symbol: MP3364GR-Z
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (None pp, sha256 2d17e143ea0f3bae, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF