An 8-channel 10-bit analog-to-digital converter with an SPI interface, in a SOIC-16, the standard way to add analog inputs to a Raspberry Pi (which has none of its own). Its successive-approximation core samples up to 200 k samples per second, and the eight inputs can be read as eight single-ended channels or four pseudo-differential pairs. A separate VREF pin sets the full-scale range, and AGND/DGND keep the analog and digital returns clean. The four-wire SPI (CS, DIN, DOUT, CLK) makes it trivial to read from any MCU. Runs 2.7-5.5 V.

Pinout

Pin	Name	Type	Function
1	CH0	input	Analog input channel 0. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH1. Sample cap ~20 pF, switch resistance ~1 kΩ.
2	CH1	input	Analog input channel 1. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH0.
3	CH2	input	Analog input channel 2. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH3.
4	CH3	input	Analog input channel 3. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH2.
5	CH4	input	Analog input channel 4. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH5.
6	CH5	input	Analog input channel 5. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH4.
7	CH6	input	Analog input channel 6. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH7.
8	CH7	input	Analog input channel 7. Single-ended input (VSS..VREF) or IN+/IN- of pseudo-differential pair with CH6.
9	DGND	power_in	Digital ground connection to internal digital circuitry. Tie to the system ground plane (typically joined to AGND at a single point near the device).
10	CS/SHDN	input	Active-low SPI chip select / shutdown input. Falling edge initiates a conversion cycle; driving high ends the conversion and places the device in low-power standby (typ. 5 nA). Must be held high between conversions.
11	DIN	input	SPI serial data input (MOSI). Used to clock in the start bit, single/differential select, and 3-bit channel configuration word. Sampled on the rising edge of CLK.
12	DOUT	output	SPI serial data output (MISO). Shifts out the 10-bit conversion result MSB-first on the falling edge of CLK. High-impedance when CS is high.
13	CLK	input	SPI serial clock input. Drives sampling and successive-approximation conversion. Max fCLK 3.6 MHz at VDD=5V, 1.35 MHz at VDD=2.7V; fCLK should stay ≥10 kHz to keep the internal sample cap from drooping.
14	AGND	power_in	Analog ground connection to internal analog circuitry. Tie to the analog ground plane; join to DGND at a single quiet point near the device.
15	VREF	input	Reference voltage input. Sets the analog input full-scale range (0..VREF). Allowed range 0.25 V ≤ VREF ≤ VDD. Typical reference current 100 µA at VREF=5V; decouple with a low-ESR capacitor.
16	VDD	power_in	Positive supply voltage, +2.7V to +5.5V. Typ IDD 425 µA at 5V / 225 µA at 2.7V; standby current 5 nA typ, 2 µA max. Bypass with a 0.1 µF ceramic to AGND close to the pin.

Key specifications

Parameter	Value
Type	8-channel SAR ADC
Resolution	10-bit
Sample rate	200 ksps (at 5 V)
Inputs	8 single-ended or 4 pseudo-differential
Interface	SPI (up to 3.6 MHz)
Reference	external VREF pin
Supply voltage	2.7-5.5 V
Package	SOIC-16

Ordering variants

Same part, different packaging or reel option.

MCP3008-I/SL (SOIC-16)
MCP3008-I/P (PDIP-16)

CAD (KiCad official)

Symbol: Analog_ADC:MCP3008
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Technology datasheet (40 pp, sha256 e6c2231de727395f, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF