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MC74HC540ADWG

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by Ray

onsemi Buffers, Drivers, Receivers, Transceivers, SOIC-20-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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MC74HC540ADWG

onsemi · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil

MC74HC540ADWG from onsemi, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable 1. ANDed with OE2; when both are low, the eight Y outputs are enabled as inverters. If either OE is high, all Y outputs go to high impedance.
2 A1 input Data input 1. Inverted and driven onto Y1 (pin 18) when the outputs are enabled. CMOS-compatible input; VIH >= 3.15 V, VIL <= 1.35 V at VCC = 4.5 V.
3 A2 input Data input 2. Inverted and driven onto Y2 (pin 17) when the outputs are enabled.
4 A3 input Data input 3. Inverted and driven onto Y3 (pin 16) when the outputs are enabled.
5 A4 input Data input 4. Inverted and driven onto Y4 (pin 15) when the outputs are enabled.
6 A5 input Data input 5. Inverted and driven onto Y5 (pin 14) when the outputs are enabled.
7 A6 input Data input 6. Inverted and driven onto Y6 (pin 13) when the outputs are enabled.
8 A7 input Data input 7. Inverted and driven onto Y7 (pin 12) when the outputs are enabled.
9 A8 input Data input 8. Inverted and driven onto Y8 (pin 11) when the outputs are enabled. Note: per datasheet, unused inputs must be tied high or low, not left floating.
10 GND power_in Ground reference (0 V). DC ground current per pin rated at +/-75 mA maximum.
11 Y8 tri_state 3-state inverting output 8. Drives the logical inverse of A8 (pin 9) when both OE1 and OE2 are low; enters high impedance otherwise. Sources/sinks up to 7.8 mA at VCC = 6.0 V (15 LSTTL loads).
12 Y7 tri_state 3-state inverting output 7. Drives the logical inverse of A7 (pin 8) when both OE1 and OE2 are low; high impedance otherwise.
13 Y6 tri_state 3-state inverting output 6. Drives the logical inverse of A6 (pin 7) when both OE1 and OE2 are low; high impedance otherwise.
14 Y5 tri_state 3-state inverting output 5. Drives the logical inverse of A5 (pin 6) when both OE1 and OE2 are low; high impedance otherwise.
15 Y4 tri_state 3-state inverting output 4. Drives the logical inverse of A4 (pin 5) when both OE1 and OE2 are low; high impedance otherwise.
16 Y3 tri_state 3-state inverting output 3. Drives the logical inverse of A3 (pin 4) when both OE1 and OE2 are low; high impedance otherwise.
17 Y2 tri_state 3-state inverting output 2. Drives the logical inverse of A2 (pin 3) when both OE1 and OE2 are low; high impedance otherwise.
18 Y1 tri_state 3-state inverting output 1. Drives the logical inverse of A1 (pin 2) when both OE1 and OE2 are low; high impedance otherwise.
19 OE2 input Active-low output enable 2. ANDed with OE1; when both are low, the eight Y outputs are enabled. If either OE is high, all Y outputs go to high impedance.
20 VCC power_in Positive supply voltage, 2.0-6.0 V (referenced to GND). Absolute maximum -0.5 to +7.0 V. Bypass with a local decoupling capacitor to GND (pin 10).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-20-300mil
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • MC74HC540ADWG
  • MC74HC540ADWGDWR2G
  • MC74HC540ADWGDTR2G

CAD (KiCad official)

  • Symbol: MC74HC540ADWG
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 b5db173a13c8b12d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF