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MC74ACT373DTR2G

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by Ray

onsemi Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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MC74ACT373DTR2G

onsemi · Latches · TSSOP-20

MC74ACT373DTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output Enable, active-LOW. When LOW the O0-O7 latch outputs are driven; when HIGH the outputs are placed in the high-impedance 3-state condition.
2 O0 tri_state 3-state latch output bit 0. Reflects D0 while LE is HIGH (transparent) and holds the last latched value when LE goes LOW. Source/sink 24 mA.
3 D0 input Data input bit 0. Latched into the corresponding flip-flop on the HIGH-to-LOW transition of LE (TTL-compatible input on ACT373).
4 D1 input Data input bit 1. Latched into the corresponding flip-flop on the HIGH-to-LOW transition of LE.
5 O1 tri_state 3-state latch output bit 1. Follows D1 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
6 O2 tri_state 3-state latch output bit 2. Follows D2 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
7 D2 input Data input bit 2. Latched on the HIGH-to-LOW transition of LE.
8 D3 input Data input bit 3. Latched on the HIGH-to-LOW transition of LE.
9 O3 tri_state 3-state latch output bit 3. Follows D3 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
10 GND power_in Ground reference (0 V) for the device. Connect directly to the system ground plane.
11 LE input Latch Enable. When HIGH the latches are transparent (Q follows D); on the HIGH-to-LOW edge the current D0-D7 values are stored and held while LE remains LOW.
12 O4 tri_state 3-state latch output bit 4. Follows D4 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
13 D4 input Data input bit 4. Latched on the HIGH-to-LOW transition of LE.
14 D5 input Data input bit 5. Latched on the HIGH-to-LOW transition of LE.
15 O5 tri_state 3-state latch output bit 5. Follows D5 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
16 O6 tri_state 3-state latch output bit 6. Follows D6 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
17 D6 input Data input bit 6. Latched on the HIGH-to-LOW transition of LE.
18 D7 input Data input bit 7. Latched on the HIGH-to-LOW transition of LE.
19 O7 tri_state 3-state latch output bit 7. Follows D7 while LE is HIGH; holds when LE is LOW; high-Z when OE is HIGH.
20 VCC power_in Positive supply pin. ACT373 operates at 4.5-5.5 V (5 V nominal TTL-compatible operation). Decouple locally with a 0.1 uF capacitor to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • MC74ACT373DTR2G
  • MC74ACT373DTR2GDTG
  • MC74ACT373DTR2GDWR2G
  • MC74ACT373DTR2GDWG

CAD (KiCad official)

  • Symbol: MC74ACT373DTR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 fe8a9d1ee563cf0a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF