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Contents

README

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MC74AC259DG

onsemi · Latches · SOIC-16

MC74AC259DG from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address select input bit 0. Together with A1 and A2 selects one of eight internal latches / demultiplexer outputs Q0-Q7. CMOS-level input (VIH ≥ 2.1 V at VCC = 3.0 V; VIH ≥ 3.15 V at VCC = 4.5 V).
2 A1 input Address select input bit 1. Together with A0 and A2 selects one of eight internal latches / demultiplexer outputs Q0-Q7. CMOS-level input.
3 A2 input Address select input bit 2 (MSB). Together with A0 and A1 selects one of eight internal latches / demultiplexer outputs Q0-Q7. CMOS-level input.
4 Q0 output Addressable latch output 0 / demultiplexer output 0. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
5 Q1 output Addressable latch output 1 / demultiplexer output 1. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
6 Q2 output Addressable latch output 2 / demultiplexer output 2. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
7 Q3 output Addressable latch output 3 / demultiplexer output 3. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
8 GND power_in Ground reference (0 V). All input/output voltages are referenced to this pin.
9 Q4 output Addressable latch output 4 / demultiplexer output 4. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
10 Q5 output Addressable latch output 5 / demultiplexer output 5. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
11 Q6 output Addressable latch output 6 / demultiplexer output 6. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
12 Q7 output Addressable latch output 7 / demultiplexer output 7. Active-HIGH. Drives up to IOH = -24 mA / IOL = 24 mA at VCC = 4.5 V.
13 D input Serial data input. In addressable-latch mode, the value on D is written into the addressed latch on the LOW-to-HIGH transition of E. In demultiplex mode, D drives the addressed output. Setup ts = 3.5 ns / hold th = 2.5 ns at VCC = 3.3 V.
14 E input Active-LOW Enable / latch strobe. When E is LOW (and MR is HIGH), data on D is written into the addressed latch (addressable-latch mode). Together with MR selects operating mode per the Mode Select table.
15 MR input Active-LOW Master Reset (Common Clear). When MR = LOW and E = HIGH, all Q0-Q7 outputs are forced LOW asynchronously. Minimum pulse width tw ≈ 6.0 ns at VCC = 5.0 V.
16 VCC power_in Positive supply voltage. Operating range 2.0-6.0 V for 'AC devices (typ. 5.0 V); 4.5-5.5 V for 'ACT devices. Absolute max 7.0 V. Quiescent ICC ≤ 8 μA typ.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • MC74AC259DG
  • MC74AC259DGDR2G

CAD (KiCad official)

  • Symbol: MC74AC259DG
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 50e6dc4ad6493e07, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF