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MC33364DR2G

onsemi · AC-DC Controllers and Regulators · SOIC-16

MC33364DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Zero Current input Zero Current Detect (ZCD). Monitors the auxiliary winding voltage during the demagnetization phase and compares it to an internal 1.0 V threshold (200 mV hysteresis) to reset the RS latch and initiate MOSFET turn-on for critical-conduction operation. Internal clamps at +10 V / -0.7 V; limit input current to ~2 mA with an external resistor.
2 N/C unconnected No internal connection.
3 Current Sense input Current Sense (CS) input. Monitors primary switch current via a sense resistor. Leading-Edge Blanking (~250 ns) suppresses false triggering. Compared to VFB/4 with a ~110 mV internal offset; maximum trip level of 1.15 V limits peak drain current to 1.15 V / Rsense.
4 Voltage FB input Voltage Feedback (FB) input, typically connected to the optocoupler collector for isolated secondary feedback. Internally pulled up to Vref via a 5 kΩ resistor. Input range 1.1 V to 1.4 V; controls the CS trip threshold as VCS(max) = VFB/4 - 0.1 V.
5 N/C unconnected No internal connection.
6 Vref power_out Buffered internal 5.0 V (typ 5.05 V, min 4.90 V / max 5.20 V) voltage reference output with undervoltage lockout (~4.5 V threshold). Maximum output current 5 mA. A 0.1 µF decoupling capacitor is recommended for stability.
7 N/C unconnected No internal connection.
8 Freq Clamp input Frequency Clamp (FC) pin. Sets the minimum off-time (typ 6.9 µs when open, giving fmax ≈ 126 kHz). Tie to GND to disable the clamp (critical conduction only); tie a resistor to Vref to increase toff, or to GND to decrease toff. Threshold ~1.95 V; sink current should be kept below ~80 µA for stable operation.
9 A GND power_in Analog Ground. Ground return for the internal circuitry excluding the gate drive stage.
10 P GND power_in Power Ground. Dedicated ground return for the gate drive output stage to isolate switching currents from analog ground.
11 Gate Drive output CMOS gate-drive output for the external power MOSFET. Typical source resistance 36 Ω, sink resistance 11 Ω; rise/fall ~67/28 ns into 1 nF load. Held low during UVLO - no external pull-down needed.
12 VCC power_in Main supply for all internal circuitry including the gate drive and Vref regulator. UVLO with hysteresis: startup at 15 V (typ), shutdown at 7.6 V (typ). Absolute maximum operating voltage 16 V.
13 N/C unconnected No internal connection.
14 N/C unconnected Pin position absent - package is SOIC-16 minus pins 14 and 15 (mechanically not present on lead frame). Treated as unconnected.
15 N/C unconnected Pin position absent - package is SOIC-16 minus pins 14 and 15 (mechanically not present on lead frame). Treated as unconnected.
16 Line power_in High-voltage line input to the integrated startup current source (rated up to 700 V). Connects directly to the rectified AC bulk voltage to charge the VCC capacitor at startup, eliminating the need for external bootstrap resistors. Startup current ~8.5 mA typ.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category PMIC
Pins 16

Ordering variants

  • MC33364DR2GDG
  • MC33364DR2G
  • MC33364DR2GD1G
  • MC33364DR2GD1R2G
  • MC33364DR2GD2G
  • MC33364DR2GD2R2G

CAD (KiCad official)

  • Symbol: MC33364DR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 30ae7c27d7435187, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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