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README

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MAX16993ATJA

Analog Devices Inc Maxim Integrated · DC-DC Converters · TQFN-32-EP(5x5)

MAX16993ATJA from Analog Devices Inc Maxim Integrated, in a TQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PV1 power_in Supply input for Buck 1 low-side gate drive. Bypass to GND with ≥0.1µF ceramic capacitor. Range -0.3V to +6.0V.
2 DL1 output Low-side gate-drive output for Buck 1. Swings from GND to VPV1 (~5V).
3 GND power_in Power ground for Buck 1 driver stage. Tie to the system ground plane along with PGND2, PGND3, and EP.
4 LX1 passive Buck 1 inductor / switching node. Connect to the switched side of the external inductor; also serves as the return rail for the DH1 high-side driver. Range -6.0V to VSUP+6.0V.
5 DH1 output High-side gate-drive output for Buck 1. Swings from VLX1 to VBST1 (bootstrapped ~5V above LX1).
6 BST1 passive Bootstrap capacitor connection for the Buck 1 high-side gate drive. Connect a high-voltage diode from BIAS to BST1 and a ceramic capacitor between BST1 and LX1. BST1-LX1 range -0.3V to +6.0V.
7 VSUP power_in Main high-voltage supply input. Operating range 3.5V to 36V continuous (42V load-dump). Bypass with ≥0.1µF close to the pin.
8 EN1 input High-voltage-tolerant active-high digital enable for Buck 1. Drive high to enable OUT1. Rated -0.3V to +45V.
9 BIAS power_out 5V internal LDO output that powers the internal circuitry. Bypass to GND with ≥2.2µF low-ESR ceramic. Typ 5.0V (4.6V-5.4V).
10 PV power_in Analog supply. Connect to BIAS through a ~10Ω resistor and to GND through a 1µF ceramic capacitor.
11 FB1 input Buck 1 feedback input. In fixed-output variants tie FB1 to BIAS or GND to select factory-trimmed voltage; in adjustable option (ordered here) connect a resistor divider from OUT1, regulated to 1.0V (typ).
12 CS1 input Positive current-sense input for Buck 1. Connect to the positive terminal of the external current-sense resistor. Current-limit threshold VCS1-VOUT1 = 120mV typ.
13 OUT1 input Buck 1 output-voltage sense and negative current-sense input. Connect to the negative terminal of the sense resistor / OUT1 rail; also powers/references PV2 and PV3 in the cascaded topology.
14 EN2 input Active-high digital enable input for Buck 2. Drive high to enable OUT2.
15 EN3 input Active-high digital enable input for Buck 3. Drive high to enable OUT3.
16 OUT3 input Buck 3 output voltage-sense input. In adjustable mode (this option) connect through a resistor divider from VOUT3.
17 RESET3 output Open-drain Buck 3 reset output. Asserted low while VOUT3 is out of regulation and for the programmed active timeout after regulation. Pull up to a rail ≤5V.
18 PV3 power_in Buck 3 power input. Connect to OUT1 with a ≥2.2µF ceramic capacitor to PGND3. Range -0.3V to +6.0V.
19 LX3 passive Buck 3 switching node (drain of internal HS/LS FETs). High impedance when Buck 3 is disabled.
20 PGND3 power_in Power ground return for the Buck 3 internal FETs. Must be within ±0.3V of GND.
21 PGND2 power_in Power ground return for the Buck 2 internal FETs. Must be within ±0.3V of GND.
22 LX2 passive Buck 2 switching node (drain of internal HS/LS FETs). High impedance when Buck 2 is disabled.
23 PV2 power_in Buck 2 power input. Connect to OUT1 with a ≥2.2µF ceramic capacitor to PGND2. Range -0.3V to +6.0V.
24 RESET2 output Open-drain Buck 2 reset output. Asserted low until VOUT2 has been in regulation for the programmed active timeout. Pull up to a rail ≤5V.
25 OUT2 input Buck 2 output voltage-sense input. In adjustable mode (this option) connect through a resistor divider from VOUT2.
26 CSEL1 input Buck 1 clock select. Tie to GND for 2.1MHz operation; tie to BIAS for the OTP-programmed divide-down (e.g., 1.05MHz/525kHz/420kHz/350kHz per Selector Guide).
27 SSEN input Spread-spectrum enable. Tie to GND for a standard oscillator; tie to BIAS to enable ±3% (0 to +6%) spread-spectrum modulation of fSW.
28 RESET1 output Open-drain Buck 1 reset output. Asserted low until VOUT1 has been in regulation for the programmed active timeout. Pull up to a rail ≤5V.
29 GND power_in Analog ground reference for the controller and internal circuitry.
30 COMP1 passive Buck 1 error-amplifier compensation node. Connect an external R-C network to GND to set the loop response (see Compensation Network section).
31 ERR output Open-drain error-status output. Asserts low on a thermal-warning / thermal-shutdown event. Pull up to a rail ≤5V.
32 SYNC input External clock synchronization input. Leave open or tie to GND for skip-mode; tie to BIAS or drive with an external 1.7-2.4MHz clock for forced-PWM fixed-frequency operation.
33 EP power_in Exposed thermal pad on the package underside. Connect to the ground plane for heat removal. Does not replace the PGND2/PGND3/GND connections.

Key specifications

Parameter Value
Manufacturer Analog Devices Inc Maxim Integrated
Package TQFN-32-EP(5x5)
Category Power Management (PMIC)
Pins 33

Ordering variants

Same part, different packaging or reel option.

  • MAX16993ATJA+
  • MAX16993ATJA/V+
  • MAX16993ATJAAGJA/VY+

CAD (KiCad official)

  • Symbol: MAX16993ATJA
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: TQFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices Inc Maxim Integrated datasheet (None pp, sha256 e7f77665b839feb1, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF