component
m95040-wmn6tp
Public Unreviewedby Ray
STMicroelectronics EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownM95040-WMN6TP
STMicroelectronics · EEPROM · SOIC-8
M95040-WMN6TP from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | input | Chip Select (active-low). Driving S low selects the device and places it in Active Power mode; when S is high the device is deselected and Q is high-impedance. A falling edge on S is required after power-up before the first instruction; the S line should track VCC via a pull-up (typ. 100 kΩ) during power-up/down and must not float. |
| 2 | Q | output | Serial Data Output (MISO). Data is shifted out MSB-first on the falling edge of Serial Clock (C). Output is high-impedance when the device is deselected or in the Hold condition. |
| 3 | W | input | Write Protect (active-low). When W is held low, writes to the memory array (and to the Status Register when SRWD=1) are disabled while other operations remain enabled. W must be driven high or low - do not leave floating. |
| 4 | VSS | power_in | Ground reference for the VCC supply voltage. Connect to system ground; decouple VCC to VSS with ~10-100 nF close to the package pins. |
| 5 | D | input | Serial Data Input (MOSI). Receives instructions, addresses, and write data MSB-first; values are latched on the rising edge of Serial Clock (C). |
| 6 | C | input | Serial Clock (SCK). Provides the timing for the serial interface; supports SPI modes (CPOL=0, CPHA=0) and (CPOL=1, CPHA=1) up to 20 MHz. D is sampled on the rising edge, Q changes on the falling edge. An external pull-down (typ. 100 kΩ) is recommended so C stays low if all SPI signals go high-impedance. |
| 7 | HOLD | input | Hold (active-low). Pauses serial communication with the device without deselecting it: while HOLD is low with S also low, Q is high-impedance and D and C are Don't Care. To enter Hold, drive HOLD low while C is low; to exit, drive HOLD high while C is low. Must be driven high or low - do not leave floating. |
| 8 | VCC | power_in | Supply voltage input, 2.5 V to 5.5 V for the -W voltage grade. Must be stable within [VCC(min), VCC(max)] before issuing instructions; a power-on-reset (POR) holds the device inactive until VCC crosses the VRES threshold. Decouple to VSS with ~10-100 nF close to the package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
M95040-WMN6TPM95040-WMN6TPDWM95040-WMN6TPMC
CAD (KiCad official)
- Symbol:
M95040-WMN6TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (None pp, sha256
1b7ee07d5879b564, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).