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m74hc259yrm13tr
Public Unreviewedby Ray
STMicroelectronics Latches, SO-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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markdownM74HC259YRM13TR
STMicroelectronics · Latches · SO-16
M74HC259YRM13TR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Address input A (LSB of latch-select address). Combined with B and C, selects which of the 8 latches (Q0-Q7) is addressed. CMOS input, VIH >= 0.7VCC, VIL <= 0.3VCC (approx.). |
| 2 | B | input | Address input B (middle bit of latch-select address). Combined with A and C, selects which of the 8 latches (Q0-Q7) is addressed. |
| 3 | C | input | Address input C (MSB of latch-select address). Combined with A and B, selects which of the 8 latches (Q0-Q7) is addressed. |
| 4 | Q0 | output | Latch output 0. Addressed when C=L, B=L, A=L. Push-pull CMOS output, |
| 5 | Q1 | output | Latch output 1. Addressed when C=L, B=L, A=H. Push-pull CMOS output, |
| 6 | Q2 | output | Latch output 2. Addressed when C=L, B=H, A=L. Push-pull CMOS output, |
| 7 | Q3 | output | Latch output 3. Addressed when C=L, B=H, A=H. Push-pull CMOS output, |
| 8 | GND | power_in | Ground (0 V) reference for the device. |
| 9 | Q4 | output | Latch output 4. Addressed when C=H, B=L, A=L. Push-pull CMOS output, |
| 10 | Q5 | output | Latch output 5. Addressed when C=H, B=L, A=H. Push-pull CMOS output, |
| 11 | Q6 | output | Latch output 6. Addressed when C=H, B=H, A=L. Push-pull CMOS output, |
| 12 | Q7 | output | Latch output 7. Addressed when C=H, B=H, A=H. Push-pull CMOS output, |
| 13 | D | input | Serial data input. The logic level on D is transferred to the addressed latch (Q0-Q7) while ENABLE is low, and stored on the positive-going edge of ENABLE. |
| 14 | ~{ENABLE} | input | Latch enable input, active low. When low, data on D flows through to the addressed latch (transparent mode); when high, all latches hold their previous state. Data is latched on the positive-going edge. |
| 15 | ~{CLEAR} | input | Conditional asynchronous reset input, active low. With ENABLE high, taking CLEAR low clears all 8 latches to low. With ENABLE low, all unaddressed latches are cleared while the addressed latch follows D (3-to-8 line decoder mode). |
| 16 | VCC | power_in | Positive supply voltage. Recommended operating range 2.0 V to 6.0 V; absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
M74HC259YRM13TRM74HC259YRM13TRM74HC259RM13TRM74HC259YRM13TRM74HC259TTRM74HC259YRM13TRM74HC259YTTR
CAD (KiCad official)
- Symbol:
M74HC259YRM13TR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (None pp, sha256
972d1b43864d2b68, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).