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m24c32-wmn6tp
Public Unreviewedby Ray
STMicroelectronics EEPROM, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownM24C32-WMN6TP
STMicroelectronics · EEPROM · SOIC-8
M24C32-WMN6TP from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Chip Enable address input bit 0. Ties to VCC or VSS to set the LSB (b1) of the 7-bit I²C device select code, allowing up to eight M24C32 devices on the same bus. When left floating, this input is read as low (0). |
| 2 | E1 | input | Chip Enable address input bit 1. Ties to VCC or VSS to set bit b2 of the 7-bit I²C device select code. When left floating, this input is read as low (0). |
| 3 | E2 | input | Chip Enable address input bit 2 (MSB of the chip-enable field). Ties to VCC or VSS to set bit b3 of the 7-bit I²C device select code. When left floating, this input is read as low (0). |
| 4 | VSS | power_in | Ground reference for VCC and all logic signals. Connect to the system ground plane. |
| 5 | SDA | bidirectional | Serial Data - bidirectional, open-drain I²C data line. Transfers address and data bytes in both directions. Requires an external pull-up resistor to VCC (value depends on bus capacitance; see Figure 5). |
| 6 | SCL | input | Serial Clock - I²C clock input driven by the bus master; strobes all data in and out of the device. Supports 400 kHz fast-mode I²C. A pull-up to VCC is only required if a slave stretches the clock; otherwise a push-pull master output is sufficient. |
| 7 | WC | input | Write Control (hardware write-protect). When driven high, write operations to the entire memory array are inhibited (device-select and address bytes are still ACKed, but data bytes are not ACKed). When low or left unconnected (internally read as VIL), writes are enabled. |
| 8 | VCC | power_in | Supply voltage input, 2.5 V to 5.5 V for the M24C32-W variant. Decouple with a 10-100 nF capacitor placed close to the VCC/VSS pins. Device holds a power-on-reset (POR) until VCC crosses the POR threshold. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
M24C32-WMN6TPM24C32-WMN6TPMN3M24C32-WMN6TPMN3TM24C32-WMN6TPMN3TPM24C32-WMN6TPBN6M24C32-WMN6TPBN3M24C32-WMN6TPDW6M24C32-WMN6TPDW6TM24C32-WMN6TPDW3M24C32-WMN6TPDW3TM24C32-WMN6TPMB6M24C32-WMN6TPMB6TM24C32-WMN6TPMB3M24C32-WMN6TPMB3T
CAD (KiCad official)
- Symbol:
M24C32-WMN6TP - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (None pp, sha256
184faeb1e405d42a, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).