M0518LD2AE from Nuvoton Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PB.12/CLKO/BPWM1_CH3	bidirectional	General-purpose I/O PB.12; alternate: CLKO frequency-divider clock output and BPWM1 channel-3 output/capture input.
2	PF.5/I2C0_SCL/PWM1_CH5	bidirectional	General-purpose I/O PF.5; alternate: I2C0 clock line and PWM1 channel-5 output/capture input.
3	PF.4/I2C0_SDA/PWM1_CH4	bidirectional	General-purpose I/O PF.4; alternate: I2C0 data line and PWM1 channel-4 output/capture input.
4	PA.11/I2C1_SCL/PWM1_CH3	bidirectional	General-purpose I/O PA.11; alternate: I2C1 clock line and PWM1 channel-3 output/capture input.
5	PA.10/I2C1_SDA/PWM1_CH2	bidirectional	General-purpose I/O PA.10; alternate: I2C1 data line and PWM1 channel-2 output/capture input.
6	PA.9/I2C0_SCL/UART1_nCTS	bidirectional	General-purpose I/O PA.9; alternate: I2C0 clock line and UART1 Clear-to-Send (nCTS) input.
7	PA.8/I2C0_SDA/UART1_nRTS	bidirectional	General-purpose I/O PA.8; alternate: I2C0 data line and UART1 Request-to-Send (nRTS) output.
8	PB.4/UART1_RXD	bidirectional	General-purpose I/O PB.4; alternate: UART1 data receiver input.
9	PB.5/UART1_TXD	bidirectional	General-purpose I/O PB.5; alternate: UART1 data transmitter output.
10	LDO_CAP	passive	LDO output/decoupling pin - connect an external bypass capacitor to stabilise the on-chip 1.8 V LDO output. See Section 6.2.3 System Power Distribution.
11	VDD	power_in	Power supply for the I/O ports and LDO source for the internal PLL and digital circuitry. Operating range 2.5 V to 5.5 V.
12	VSS	power_in	Ground reference for the digital circuitry.
13	PB.0/UART0_RXD	bidirectional	General-purpose I/O PB.0; alternate: UART0 data receiver input.
14	PB.1/UART0_TXD	bidirectional	General-purpose I/O PB.1; alternate: UART0 data transmitter output.
15	PB.2/UART0_nRTS/TM2_EXT/TM2/PWM1_BRAKE1	bidirectional	General-purpose I/O PB.2; alternates: UART0 nRTS output, Timer2 external capture input, Timer2 toggle output, or PWM1 brake input 1.
16	PB.3/UART0_nCTS/TM3_EXT/TM3/PWM1_BRAKE0	bidirectional	General-purpose I/O PB.3; alternates: UART0 nCTS input, Timer3 external capture input, Timer3 toggle output, or PWM1 brake input 0.
17	PD.6/BPWM1_CH1	bidirectional	General-purpose I/O PD.6; alternate: BPWM1 channel-1 output/capture input.
18	PD.7/BPWM1_CH0	bidirectional	General-purpose I/O PD.7; alternate: BPWM1 channel-0 output/capture input.
19	PD.14/UART2_RXD/BPWM0_CH5	bidirectional	General-purpose I/O PD.14; alternate: UART2 data receiver input or BPWM0 channel-5 output/capture input.
20	PD.15/UART2_TXD/BPWM0_CH4	bidirectional	General-purpose I/O PD.15; alternate: UART2 data transmitter output or BPWM0 channel-4 output/capture input.
21	PC.3/SPI0_MOSI0/BPWM0_CH3	bidirectional	General-purpose I/O PC.3; alternate: SPI0 MOSI (Master Out, Slave In) or BPWM0 channel-3 output/capture input.
22	PC.2/SPI0_MISO0/BPWM0_CH2	bidirectional	General-purpose I/O PC.2; alternate: SPI0 MISO (Master In, Slave Out) or BPWM0 channel-2 input/capture input.
23	PC.1/SPI0_CLK/BPWM0_CH1	bidirectional	General-purpose I/O PC.1; alternate: SPI0 serial clock or BPWM0 channel-1 input/capture input.
24	PC.0/SPI0_SS0/BPWM0_CH0	bidirectional	General-purpose I/O PC.0; alternate: SPI0 slave-select 0 or BPWM0 channel-0 input/capture input.
25	PA.15/PWM0_CH3	bidirectional	General-purpose I/O PA.15; alternate: PWM0 channel-3 output/capture input.
26	PA.14/PWM0_CH2	bidirectional	General-purpose I/O PA.14; alternate: PWM0 channel-2 output/capture input.
27	PA.13/PWM0_CH1/UART5_TXD	bidirectional	General-purpose I/O PA.13; alternate: PWM0 channel-1 output/capture input or UART5 data transmitter output.
28	PA.12/PWM0_CH0/UART5_RXD	bidirectional	General-purpose I/O PA.12; alternate: PWM0 channel-0 output/capture input or UART5 data receiver input.
29	PF.7/ICE_DAT	bidirectional	General-purpose I/O PF.7; alternate: Serial-Wire Debug data pin (ICE_DAT). Used with ICE_CLK for SWD debug and 2-wire ICP.
30	PF.6/ICE_CLK	bidirectional	General-purpose I/O PF.6; alternate: Serial-Wire Debug clock pin (ICE_CLK).
31	AVSS	power_in	Ground pin for the internal analog circuitry (ADC, VREF, LDO reference).
32	PA.0/ADC_CH0/PWM0_CH4/I2C1_SCL/UART5_TXD	bidirectional	General-purpose I/O PA.0; alternates: ADC analog input channel 0, PWM0 channel-4, I2C1 clock line, or UART5 data transmitter output.
33	PA.1/ADC_CH1/PWM0_CH5/I2C1_SDA/UART5_RXD	bidirectional	General-purpose I/O PA.1; alternates: ADC analog input channel 1, PWM0 channel-5, I2C1 data line, or UART5 data receiver input.
34	PA.2/ADC_CH2/PWM1_CH0/UART3_TXD	bidirectional	General-purpose I/O PA.2; alternates: ADC analog input channel 2, PWM1 channel-0, or UART3 data transmitter output.
35	PA.3/ADC_CH3/PWM1_CH1/UART3_RXD	bidirectional	General-purpose I/O PA.3; alternates: ADC analog input channel 3, PWM1 channel-1, or UART3 data receiver input.
36	PA.4/ADC_CH4	bidirectional	General-purpose I/O PA.4; alternate: ADC analog input channel 4.
37	PA.5/ADC_CH5/UART3_RXD	bidirectional	General-purpose I/O PA.5; alternates: ADC analog input channel 5 or UART3 data receiver input.
38	PA.6/ADC_CH6/UART3_TXD	bidirectional	General-purpose I/O PA.6; alternates: ADC analog input channel 6 or UART3 data transmitter output.
39	PA.7/ADC_CH7/VREF	bidirectional	General-purpose I/O PA.7; alternates: ADC analog input channel 7 or external ADC voltage reference (VREF) input.
40	AVDD	power_in	Power supply for the internal analog circuitry (ADC and reference). Should be tied to VDD with proper filtering.
41	PC.7/UART4_RXD/I2C0_SCL/PWM0_BRAKE1	bidirectional	General-purpose I/O PC.7; alternates: UART4 data receiver input, I2C0 clock line, or PWM0 brake input 1.
42	PC.6/UART4_TXD/I2C0_SDA/PWM0_BRAKE0	bidirectional	General-purpose I/O PC.6; alternates: UART4 data transmitter output, I2C0 data line, or PWM0 brake input 0.
43	PB.15/INT1/TM0_EXT/TM0/BPWM1_CH5	bidirectional	General-purpose I/O PB.15; alternates: external interrupt 1 (INT1) input, Timer0 external capture input, Timer0 toggle output, or BPWM1 channel-5 output/capture input.
44	PF.0/XT1_OUT	bidirectional	General-purpose I/O PF.0; alternate: external 4-24 MHz high-speed crystal output (XT1_OUT). Connect to the far side of the HXT crystal.
45	PF.1/XT1_IN	bidirectional	General-purpose I/O PF.1; alternate: external 4-24 MHz high-speed crystal input (XT1_IN).
46	nRESET	input	External reset input; active-LOW with an internal pull-up. Driving this pin low resets the chip to its initial state.
47	PF.8/CLKO/BPWM1_CH4	bidirectional	General-purpose I/O PF.8; alternates: CLKO frequency-divider clock output or BPWM1 channel-4 output/capture input.
48	PB.8/STADC/TM0/CLKO/BPWM1_CH2	bidirectional	General-purpose I/O PB.8; alternates: ADC external trigger input (STADC), Timer0 event counter input/toggle output, CLKO frequency-divider clock output, or BPWM1 channel-2 output/capture input.

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	LQFP-48(7x7)
Category	MCU
Pins	48

Ordering variants

Same part, different packaging or reel option.

M0518LC2AE
M0518LD2AE
M0518SC2AE
M0518SD2AE

CAD (KiCad official)

Symbol: M0518LD2AE
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`m0518ld2ae.step`	617 KB	You want the bare part, or you mark your own boards.
`m0518ld2ae-etched.step`	4.0 MB	You want the part with `M0518LD2AE` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1021 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (72 pp, sha256 e3b686c638ac418e, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF