Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

LP6222SPF

LOWPOWER · DC-DC Converters · ESOP-8

LP6222SPF from LOWPOWER, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground return. Connect to system ground plane; tie together with pins 5 and the exposed pad (pin 9) for low-impedance return of the switching current.
2 FB input Regulation feedback input. Connect an external resistive voltage divider from VOUT to FB to program the output voltage; the internal reference is 0.6 V so VOUT = (R1/R2 + 1) x 0.6 V.
3 LX power_out Switching node. Connect to the boost inductor and the anode of the Schottky rectifier. Rated to 12 V max relative to GND; keep trace short to minimize EMI. Tied to pin 4 internally to share switching current.
4 LX power_out Switching node (paralleled with pin 3). Both LX pins should be tied together at the inductor for the full 4.8 A switch current rating.
5 GND power_in Ground return (paralleled with pin 1 and the exposed thermal pad on pin 9).
6 ISET input Peak switch current programming input. A resistor R3 between ISET and GND (10 kΩ to 96 kΩ) sets the cycle-by-cycle current limit from 4.8 A down to 0.5 A per IOCP = 48000 / R3. Keep trace short; do not add capacitance on this pin.
7 VIN power_in Input supply. Operating range 2.5 V to 5.5 V (6 V absolute max). Bypass with a 22 μF low-ESR ceramic capacitor to GND placed close to the pin.
8 EN input Enable/shutdown control input. VEN > 1.4 V enables the regulator; VEN < 0.4 V forces low-current shutdown (<1 μA). Do not leave floating.
9 GND power_in Exposed thermal pad on the ESOP-8 underside. Must be soldered to the ground plane for thermal dissipation (θJA ≈ 50 °C/W); electrically tied to GND (pins 1 and 5).

Key specifications

Parameter Value
Manufacturer LOWPOWER
Package ESOP-8
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • LP6222SPF
  • LP6222SPFB6F

CAD (KiCad official)

  • Symbol: LP6222SPF
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
lp6222spf.step 125 KB You want the bare part, or you mark your own boards.
lp6222spf-etched.step 2.0 MB You want the part with LP6222SPF already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 494 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LOWPOWER datasheet (9 pp, sha256 29f15cc49a61383e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF