component
LP4078QVF
Public Unreviewedby Ray
LOWPOWER Battery Management, DFN-10-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLP4078QVF
LOWPOWER · Battery Management · DFN-10-EP(3x3)
LP4078QVF from LOWPOWER, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply source, typically connected to a wall adaptor. Operating range 4.5V-6V; withstands up to 40V (absolute max) with 22V OVP threshold. Bypass to GND with a 1-10 uF ceramic capacitor. |
| 2 | CHRG | output | Open-drain charge status output. Internal NMOS pulls the pin low while charging; goes high impedance when the charge cycle completes. Maximum sink current ~5 mA; requires an external pull-up resistor for logic-high state (typ. LED + 1k to BAT). |
| 3 | PG | output | Open-drain power-good status output. Pulls low when VIN is above the UVLO threshold and above VBAT+150 mV, and below the OVP threshold; Hi-Z otherwise. Requires an external pull-up; max sink 5 mA. |
| 4 | EN | input | Charge enable input (active low). Logic-low (<0.4V) or floating enables charging; logic-high (>1.4V) puts the device in shutdown. Tie to GND if the enable function is not needed. |
| 5 | NTC | input | NTC thermistor input for battery temperature monitoring per JEITA. Uses an internal 48 uA bias current with a 10k NTC (B=3370) between NTC and GND. Thresholds correspond to 0/10/60 °C; charge is halved between 0-10 °C and disabled below 0 °C or above 60 °C. Tie via a fixed 10k resistor to GND to disable the feature. |
| 6 | GND | power_in | Device ground. Connect to the system ground plane together with pin 11 (exposed pad). |
| 7 | NC | unconnected | No internal connection. Leave floating or tie to GND for best PCB layout. |
| 8 | IBF | passive | Charge termination current threshold program pin. Connect a resistor R_IBF from IBF to GND; termination current I_BF = (R_ISET x I_BAT) / R_IBF. Example: R_ISET=1.7k, R_IBF=17k -> 100 mA termination. |
| 9 | ISET | passive | Constant charge current program pin. Connect a resistor R_ISET from ISET to GND; constant current I_BAT = V_ISET x 1700 / R_ISET (V_ISET = 1V typ). R_ISET=1.7k gives ~1000 mA; R_ISET=3.4k gives ~500 mA. |
| 10 | BAT | power_out | Battery pin. Connect to the single-cell Li-Ion/Li-Polymer battery positive terminal. Regulated float voltage 4.20V/4.35V/4.40V per ordering suffix; withstand up to 15V absolute max. Bypass with a 1-10 uF capacitor placed close to the pin. |
| 11 | GND (PAD) | power_in | Exposed thermal pad on the package underside. Must be soldered to the PCB ground plane for electrical ground and thermal dissipation; add multiple vias to the ground plane to spread heat. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LOWPOWER |
| Package | DFN-10-EP(3x3) |
| Category | PMIC |
| Pins | 11 |
Ordering variants
Same part, different packaging or reel option.
LP4078QVFLP4078QVF-435LP4078QVF-440
CAD (KiCad official)
- Symbol:
LP4078QVF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LOWPOWER datasheet (11 pp, sha256
449276d21b78d6f5, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).