LP4076HSPF-435
Public Unreviewedby Ray
LOWPOWER Battery Management, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownLP4076HSPF-435
LOWPOWER · Battery Management · ESOP-8
LP4076HSPF-435 from LOWPOWER, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TS | input | Battery temperature-detection input. Sensed against an internal resistor divider with thresholds at 60%VIN (cold) and 30%VIN (hot). Tie to GND or hold below 0.3V (VTS_DIS) to disable the TS function. |
| 2 | ISET | passive | Charge-current program pin. Connect a 1% resistor RISET from ISET to GND; IBAT = 1700 x VISET / RISET (VISET typ 1V). Also used internally for termination detection when the pin voltage falls below 100mV. |
| 3 | GND | power_in | System ground. Must be tied together with pin 9 (exposed pad) to the board ground plane. |
| 4 | IN | power_in | Input power supply from a wall adapter. Operating range 4.5V-6V typ; absolute maximum 28V with internal OVP disabling the charger above ~7V (VOVP). UVLO rising threshold 3.5V. |
| 5 | BAT | power_out | Battery connection and charger output. Regulated float voltage 4.35V (LP4076HSPF-435). Requires a 1uF ceramic cap with a battery attached, or a 10uF tantalum cap for stability when no battery is present. Absolute maximum -5V to 15V. |
| 6 | FULL | output | Open-drain charge-status output. High-Z (external pull-up to VCC) while charging; pulled low by internal N-MOS when the charge cycle completes. VOL <= 0.5V at 5mA. |
| 7 | CHRG | output | Open-drain charge-status output. Pulled low by internal N-MOS while charging; goes high-impedance (external pull-up to VCC) when the charge cycle completes. VOL <= 0.5V at 5mA. |
| 8 | EN | input | Charge enable input, active high. VIH >= 1.4V, VIL <= 0.4V. Drive high to enable charging, low to shut down. |
| 9 | GND | power_in | Exposed thermal pad on the bottom of the ESOP-8. Electrically connected to GND; must be soldered to the board ground plane for proper thermal performance and low-impedance ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LOWPOWER |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
LP4076HSPF-435
CAD (KiCad official)
- Symbol:
LP4076HSPF-435 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
lp4076hspf-435.step |
125 KB | You want the bare part, or you mark your own boards. |
lp4076hspf-435-etched.step |
2.6 MB | You want the part with LP4076HSPF-435 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 641 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LOWPOWER datasheet (9 pp, sha256
6a7c9b070a7052a8, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).