component
LP2951CDR2G
Public Unreviewedby Ray
onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLP2951CDR2G
onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
LP2951CDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT | power_out | Regulated output. Sources up to 100 mA. Requires a 1.0 uF (or larger) output capacitor for stability. Internally current- and thermally-limited. |
| 2 | SENSE | input | Output-voltage sense input for the internal fixed-voltage divider. Connect to the OUTPUT pin (pin 1) at the load to Kelvin-sense the regulated rail when using the internal preset divider. In fixed-output mode the internal 182 k/60 k divider taps into this node. |
| 3 | SHUTDOWN | input | Logic-level shutdown input. Logic 0 (0 to 0.7 V) enables the regulator; Logic 1 (2.0 to 30 V) disables the pass transistor, dropping quiescent current. Input current ~35 uA typical at 2.4 V, ~450 uA at 30 V. Absolute max -0.3 to +30 V. |
| 4 | GND | power_in | Device ground reference and return for the internal 1.23 V bandgap, error amplifier, and error comparator. |
| 5 | ERROR | output | Open-collector error flag output (active low). Pulls low when the regulated output drops ~5% below its nominal value (out-of-regulation) or during current/thermal limiting. Requires an external pull-up to a logic rail (max 30 V). VOL <= 250 mV at 400 uA; leakage <= 1.0 uA at VOH = 30 V. Useful as a microprocessor power-on reset. |
| 6 | VO_TAP | passive | Direct tap into the top of the internal feedback resistor divider (nominally 1.235 V reference multiplied by the divider ratio at the output). Typically connected to the top of an external programming resistor divider when using the adjustable configuration, or left as the VO tap in fixed-voltage operation. |
| 7 | FEEDBACK | input | Error-amplifier inverting feedback input. Connect to the divider tap in adjustable mode (Vout = 1.235 V x (1 + R1/R2), programmable 1.25 V to 29 V). Feedback bias current ~15 nA typical, 40 nA max. Absolute max -1.5 to +30 V. |
| 8 | INPUT | power_in | Unregulated supply input, VCC. Absolute maximum 30 Vdc (32 V transient, t < 20 ms). Must be at least Vout + dropout (~50 mV at 100 uA, ~380 mV at 100 mA). Bypass locally for stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
LP2951CDR2GLP2951CDR2GACDLP2951CDR2GACDR2LP2951CDR2GACDR2GLP2951CDR2GCNLP2951CDR2GACNLP2951CDR2GCDMLP2951CDR2GACDMLP2951CDR2GCZLP2951CDR2GACZLP2951CDR2GCDTLP2951CDR2GACDT
CAD (KiCad official)
- Symbol:
LP2951CDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
lp2951cdr2g.step |
122 KB | You want the bare part, or you mark your own boards. |
lp2951cdr2g-etched.step |
2.3 MB | You want the part with LP2951CDR2G already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 566 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (22 pp, sha256
bb301a5f833e5fda, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).