component
LMR23625CFDDAR
Public Unreviewedby Ray
Texas Instruments DC-DC Converters, SO-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLMR23625CFDDAR
Texas Instruments · DC-DC Converters · SO-8-EP
LMR23625CFDDAR from Texas Instruments, in a SO-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | power_out | Switching output of the regulator, internally connected to the source of the high-side MOSFET and the drain of the low-side MOSFET. Connect to the power inductor. Rated -1 V to VIN+0.3 V (abs max), -5 V to 42 V for <10-ns transients. |
| 2 | BOOT | passive | Bootstrap capacitor connection for the high-side gate driver. Connect a 100 nF to 470 nF high-quality ceramic capacitor from BOOT to SW. Max BOOT-to-SW voltage 5.5 V. |
| 3 | VCC | power_out | Internal bias LDO output for bypassing. Connect a 2.2-µF, 16-V bypass capacitor from this pin to AGND. Do not load externally and do not short to ground during operation. Max 4.5 V (5.25 V in shutdown). |
| 4 | FB | input | Feedback input to the error amplifier. Connect the midpoint of the output feedback resistor divider to this pin. Reference voltage VREF = 1.0 V (typ). Recommended operating range -0.3 V to 1.2 V. |
| 5 | EN/SYNC | input | Enable input to the regulator; high = ON, low = OFF, may be tied to VIN. Do not float. Also serves as an external clock synchronization input: coupling a positive pulse through a small capacitor synchronizes the internal oscillator. Enable rising threshold 1.55 V (typ); recommended range -5 V to 36 V. |
| 6 | AGND | power_in | Analog ground pin. Ground reference for internal references and control logic. Must be connected to system ground (bond to PGND / PAD on the PCB). |
| 7 | VIN | power_in | Input supply pin. Operating range 4 V to 36 V (abs max 42 V). Requires a low-ESR ceramic input capacitor to PGND placed as close to the pin as possible. |
| 8 | PGND | power_in | Power ground pin, connected internally to the source of the low-side power FET. Connect to system ground and to the ground pins of the input and output capacitors; keep the path to CIN as short as possible. |
| 9 | PAD | power_in | Exposed thermal PowerPAD on the bottom of the package. Low-impedance connection to AGND internally; must be connected to PGND on the PCB and used as the primary heat-sinking path to a ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
LMR23625CFDDARLMR23625CFDDARCDDALMR23625CFDDARCDDARLMR23625CFDDARCFPDRRLMR23625CFDDARCFPDRRR
CAD (KiCad official)
- Symbol:
LMR23625CFDDAR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8-EP (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
c36797b84ad8701d, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).