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LMK1C1108PWR

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by Ray

Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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LMK1C1108PWR

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-16

LMK1C1108PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input Single-ended LVCMOS clock input. Contains an internal 300-kΩ (typical) pulldown resistor to GND. Typically connected to a single-ended clock source; VIH = 0.7 x VDD, VIL = 0.3 x VDD; supports DC to 250 MHz at 3.3 V (DC to 200 MHz at 2.5/1.8 V).
2 1G input Global Output Enable with internal 300-kΩ (typical) pulldown resistor to GND. HIGH enables all Yn outputs; LOW disables (drives outputs low). Typically tied to VDD via an external pullup for always-on operation. Fail-safe input prevents output oscillation when CLKIN is absent.
3 Y0 output LVCMOS clock output 0. Buffered copy of CLKIN; typically drives a downstream receiver. Unused outputs may be left floating. Output impedance ≈ 50 Ω at 3.3 V.
4 GND power_in Device ground reference.
5 VDD power_in Core supply pin. Accepts 3.3 V, 2.5 V, or 1.8 V (recommended 1.71-3.465 V, absolute max 3.6 V). Bypass locally with a 0.1-µF ceramic capacitor.
6 Y4 output LVCMOS clock output 4. Buffered copy of CLKIN. Unused outputs may be left floating.
7 GND power_in Device ground reference.
8 Y6 output LVCMOS clock output 6. Buffered copy of CLKIN. Unused outputs may be left floating.
9 Y7 output LVCMOS clock output 7. Buffered copy of CLKIN. Unused outputs may be left floating.
10 VDD power_in Core supply pin (parallel-connected to the other VDD pins). Accepts 3.3 V, 2.5 V, or 1.8 V. Bypass locally with a 0.1-µF ceramic capacitor.
11 Y5 output LVCMOS clock output 5. Buffered copy of CLKIN. Unused outputs may be left floating.
12 GND power_in Device ground reference.
13 Y2 output LVCMOS clock output 2. Buffered copy of CLKIN. Unused outputs may be left floating.
14 VDD power_in Core supply pin (parallel-connected to the other VDD pins). Accepts 3.3 V, 2.5 V, or 1.8 V. Bypass locally with a 0.1-µF ceramic capacitor.
15 Y3 output LVCMOS clock output 3. Buffered copy of CLKIN. Unused outputs may be left floating.
16 Y1 output LVCMOS clock output 1. Buffered copy of CLKIN. Unused outputs may be left floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Clock/Timing
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • LMK1C1106PWR
  • LMK1C1106PW
  • LMK1C1108PWR

CAD (KiCad official)

  • Symbol: LMK1C1108PWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 9cb5952511434900, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF