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LMK1C1106PWR

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by Ray

Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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LMK1C1106PWR

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-14

LMK1C1106PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input Single-ended LVCMOS clock input. Contains an internal 300-kΩ (typical) pulldown resistor to GND. Accepts DC to 250 MHz at VDD = 3.3 V (200 MHz at 2.5 V / 1.8 V). VIH = 0.7 × VDD, VIL = 0.3 × VDD.
2 1G input Global output enable input with internal 300-kΩ (typical) pulldown resistor to GND. HIGH enables all Yn outputs; LOW forces outputs to a low state. Typically pulled up to VDD with an external resistor.
3 Y0 output LVCMOS clock output 0. Typically connected to a receiver; unused outputs can be left floating. Output impedance ≈ 50 Ω; VOH ≥ 2.8 V at IOH = 1 mA (VDD = 3.3 V).
4 GND power_in Device ground reference. Tie to system ground plane.
5 VDD power_in Core supply pin. Accepts 3.3 V, 2.5 V, or 1.8 V (typical, ±5%). Bypass with an external 0.1-µF capacitor placed near the pin.
6 Y4 output LVCMOS clock output 4. Typically connected to a receiver; unused outputs can be left floating. Output impedance ≈ 50 Ω.
7 GND power_in Device ground reference. Tie to system ground plane.
8 VDD power_in Core supply pin. Accepts 3.3 V, 2.5 V, or 1.8 V (typical, ±5%). Bypass with an external 0.1-µF capacitor placed near the pin.
9 Y5 output LVCMOS clock output 5. Typically connected to a receiver; unused outputs can be left floating. Output impedance ≈ 50 Ω.
10 GND power_in Device ground reference. Tie to system ground plane.
11 Y2 output LVCMOS clock output 2. Typically connected to a receiver; unused outputs can be left floating. Output impedance ≈ 50 Ω.
12 VDD power_in Core supply pin. Accepts 3.3 V, 2.5 V, or 1.8 V (typical, ±5%). Bypass with an external 0.1-µF capacitor placed near the pin.
13 Y3 output LVCMOS clock output 3. Typically connected to a receiver; unused outputs can be left floating. Output impedance ≈ 50 Ω.
14 Y1 output LVCMOS clock output 1. Typically connected to a receiver; unused outputs can be left floating. Output impedance ≈ 50 Ω.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Clock/Timing
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • LMK1C1106PWR

CAD (KiCad official)

  • Symbol: LMK1C1106PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 9cb5952511434900, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF