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LM5175PWPR

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by Ray

Texas Instruments DC-DC Converters, HTSSOP-28. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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LM5175PWPR

Texas Instruments · DC-DC Converters · HTSSOP-28

LM5175PWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN/UVLO input Enable / undervoltage lockout input. EN/UVLO < 0.4 V: shutdown. 0.7 V < EN/UVLO < 1.23 V: standby (VCC regulator on, PWM off). EN/UVLO > 1.23 V: PWM enabled (provided VCC exceeds its UV threshold).
2 VIN power_in Input supply pin to the IC. Connect to a supply voltage between 3.5 V and 42 V (60 V absolute max).
3 VISNS input VIN sense input. Connect to the input capacitor.
4 MODE input Operating mode select via RMODE resistor to GND or VCC. Options: GND=DCM/hiccup disabled; 49.9 kΩ to GND=DCM/hiccup enabled; 93.1 kΩ to GND=CCM/hiccup enabled; tied to VCC=CCM/hiccup disabled.
5 DITH input Dithering programming pin. A capacitor between DITH and AGND is charged/discharged by a 10 µA current source, modulating fSW by ±5%. Ground DITH to disable dithering; in external sync mode DITH is ignored.
6 RT/SYNC input Switching-frequency programming / external clock sync pin. Resistor from RT/SYNC to AGND sets fSW (100-600 kHz); can also be driven by an external clock for synchronization.
7 SLOPE passive Slope-compensation programming pin. A capacitor between SLOPE and AGND provides the slope-compensation ramp for stable current-mode operation in both buck and boost modes.
8 SS passive Soft-start programming pin. A capacitor between SS and AGND programs the soft-start time (charged by ~5.65 µA).
9 COMP output Error amplifier output. External RC network between COMP and AGND compensates the regulator feedback loop.
10 AGND power_in Analog ground reference for the IC. Tie to the system ground plane; also the return for the exposed PowerPAD.
11 FB input Feedback pin for output voltage regulation. Connect a resistor divider from VOUT to FB; internal reference is 0.800 V. OVP triggers at ~0.86 V, PGOOD window ±10%.
12 VOSNS input VOUT sense input. Connect to the output capacitor for output-side sensing.
13 ISNS(-) input Negative input of the average current-sense amplifier. Used with ISNS(+) across an optional current-sense resistor on the input or output side for constant-current (CC) control. Short ISNS(+) and ISNS(-) together to disable.
14 ISNS(+) input Positive input of the average current-sense amplifier. CC loop activates when VISNS(+)-ISNS(-) reaches ~50 mV (average current-limit target).
15 CSG input Negative (ground) input of the PWM current-sense amplifier. Connect directly to the low-side ground of the current-sense resistor.
16 CS input Positive input to the PWM current-sense amplifier. Senses inductor/switch current for cycle-by-cycle peak current-mode control.
17 PGOOD output Power-Good open-drain output. Pulled low when FB is outside a 0.8 V ±10% regulation window. Sink capability ~4.2 mA at 0.4 V; requires external pull-up.
18 SW2 power_out Boost-side switching node. Connect to the inductor and the source of the high-side boost MOSFET / drain of the low-side boost MOSFET. Also the SW reference for BOOT2/HDRV2.
19 HDRV2 output High-side gate-driver output for the boost-side MOSFET. Peak source/sink ~1.8 A / 2.2 A; connect directly to the MOSFET gate.
20 BOOT2 power_in Bootstrap supply for the boost-side high-side gate driver. Connect a capacitor between BOOT2 and SW2; 68 V absolute max to GND.
21 LDRV2 output Low-side gate-driver output for the boost-side MOSFET. Connect directly to the MOSFET gate; referenced to PGND.
22 PGND power_in Power ground of the IC. High-current ground return for the low-side gate drivers.
23 VCC power_out Output of the internal VCC bias regulator (~7.35 V typ). Bypass with a capacitor to ground; supplies the gate drivers and internal analog.
24 BIAS power_in Optional input to the VCC bias regulator. Powering VCC from an external supply (rather than VIN) reduces power loss at high VIN. For VBIAS > ~8 V the VCC regulator draws from BIAS. VBIAS must not exceed 40 V.
25 LDRV1 output Low-side gate-driver output for the buck-side MOSFET. Connect directly to the MOSFET gate; referenced to PGND.
26 BOOT1 power_in Bootstrap supply for the buck-side high-side gate driver. Connect a capacitor between BOOT1 and SW1; 68 V absolute max to GND.
27 HDRV1 output High-side gate-driver output for the buck-side MOSFET. Peak source/sink ~1.8 A / 2.2 A; connect directly to the MOSFET gate.
28 SW1 power_out Buck-side switching node. Connect to the inductor and the source of the buck-side high-side MOSFET / drain of the buck-side low-side MOSFET. Also the SW reference for BOOT1/HDRV1.
29 PAD power_in Exposed thermal PowerPAD on the underside of the HTSSOP-28 package. Solder to the analog ground copper pour and use thermal vias to an internal ground plane for heat dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28
Category PMIC
Pins 29

Ordering variants

Same part, different packaging or reel option.

  • LM5175PWPR
  • LM5175PWPRRHF
  • LM5175PWPRRHFR

CAD (KiCad official)

  • Symbol: LM5175PWPR
  • Footprint: Package_SO:HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 c2cf8e014f0da459, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF