LM5000-3MTCX from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Compensation network connection. Output of the internal voltage error amplifier. RC compensation network is tied from this pin to AGND, with an additional 100pF high-frequency capacitor to AGND recommended. VCOMP OVP trip typ 0.67V.
2	FB	input	Output voltage feedback input to the error amplifier. Regulates to VFB = 1.259V (typ). FB pin bias current 55nA typ (200nA max).
3	SHDN	input	Shutdown control input (active low, overbar in datasheet). Open = enable, Ground = disable. Threshold: high >=0.9V, low <=0.3V. Shutdown pin current -1uA typ at VSHDN=0V.
4	AGND	power_in	Analog ground. Must be connected directly to PGND at a single reference point to minimize noise coupling into the compensation and feedback networks.
5	PGND	power_in	Power ground. Return path for the internal power switch. All four PGND pins (5,6,7,8) must be tied together to the ground plane close to the SW pins.
6	PGND	power_in	Power ground. Return path for the internal power switch. All four PGND pins (5,6,7,8) must be tied together to the ground plane close to the SW pins.
7	PGND	power_in	Power ground. Return path for the internal power switch. All four PGND pins (5,6,7,8) must be tied together to the ground plane close to the SW pins.
8	PGND	power_in	Power ground. Return path for the internal power switch. All four PGND pins (5,6,7,8) must be tied together to the ground plane close to the SW pins.
9	SW	output	Power switch output. Drain of the internal NMOS power switch, connected between the SW pins and PGND pins. 80V breakdown, 2A current limit, RDS(ON) 160 mOhm typ. Tie all three SW pins (9,10,11) together.
10	SW	output	Power switch output. Drain of the internal NMOS power switch, connected between the SW pins and PGND pins. Tie all three SW pins (9,10,11) together.
11	SW	output	Power switch output. Drain of the internal NMOS power switch, connected between the SW pins and PGND pins. Tie all three SW pins (9,10,11) together.
12	BYP	passive	Bypass / decoupling capacitor connection for the internal bias rail. Connect a 0.1uF ceramic capacitor from this pin to ground.
13	VIN	power_in	Analog power input, 3.1V to 40V operating range (absolute max 40V). A small RC filter (typ 10 ohm and >=0.1uF) is recommended between the main supply and this pin to suppress line glitches.
14	SS	passive	Softstart input. An external capacitor and an internal 11uA (typ) current source set the softstart ramp time.
15	FS	input	Switching frequency select input. Open = Fhigh (700kHz on LM5000-3, 1.3MHz on LM5000-6). Ground = Flow (300kHz on LM5000-3, 600kHz on LM5000-6).
16	TEST	input	Factory test pin. Connect to ground for normal operation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

LM5000-3MTCX
LM5000-3MTCXSD

CAD (KiCad official)

Symbol: LM5000-3MTCX
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (26 pp, sha256 d8b76275b8b792ee, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF