LGS63042EP from Legend Si, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No external component required. Datasheet recommends grounding the pin.
2	GND	power_in	Ground pin. Common return for the controller and switch. Also connects to the exposed thermal pad on the ESOP-8 package.
3	SW	power_out	Internal power switch node (drain of the integrated 350mΩ low-side MOSFET). Externally connected to the power inductor and Schottky diode. Absolute max SW-to-GND voltage is 60V; max switch current 3A.
4	SW	power_out	Internal power switch node (second SW pin, tied to pin 3). Provides additional current-handling capacity and heat sinking for the SW node.
5	VIN/OUT	power_in	Output voltage detection point or input voltage connection point. Connects the LED current sampling resistor Rsense to the CSN end. Acts as an input voltage detection point in buck circuits and as an output voltage connection point in boost and lift applications. Operating input range 3.0V-60V (abs max 60V).
6	CSN	input	LED current detection pin. Connect to external LED current sampling resistor Rsence. Output current is set by IOUT = (VOUT(VIN) − VCSN) / Rsence, with typical (VOUT − VCSN) = 0.2V. Absolute max voltage: VIN−6V to VIN+0.3V.
7	OVP	input	Overvoltage protection pin. Connect to the output through a resistor divider (R1 to VOUT, R2 to GND). OVP trip is typically 1.0V (recovery 0.9V); trip output voltage set by VOUT_OVP = (1 + R1/R2) × 1.0V. Absolute max OVP-to-GND voltage: 6V.
8	EN	input	Enable / dimming input. For LGS63042 (PWM variant) drive with a digital PWM signal at 100Hz-100kHz; duty cycle sets the average LED current per IOUT = (0.2 × D) / Rsence. Rising threshold 0.5V (typ), falling 0.35V (typ), 800kΩ internal pull-down. Absolute max EN-to-GND: 6V. Do not leave floating.

Key specifications

Parameter	Value
Manufacturer	Legend Si
Package	ESOP-8
Category	LED-drv
Pins	8

Ordering variants

Same part, different packaging or reel option.

LGS63042EP
LGS63042EPB5

CAD (KiCad official)

Symbol: LGS63042EP
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
3D model: ESOP-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`lgs63042ep.step`	193 KB	You want the bare part, or you mark your own boards.
`lgs63042ep-etched.step`	2.0 MB	You want the part with `LGS63042EP` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 494 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Legend Si datasheet (22 pp, sha256 13f24f98441db88d, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF