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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs lgs63042ep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
lgs63042ep-etched.fit.json lgs63042ep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
lgs63042ep-etched.glb lgs63042ep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
lgs63042ep-etched.step lgs63042ep: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
lgs63042ep.glb fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body regenerated from the footprint F.Fab outline) · Ray 1mo ago
lgs63042ep.kicad_mod Publish 0.1.0 · Ray 1mo ago
lgs63042ep.kicad_sym add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'ESOP-8' denotes an exposed pad) · Ray 1mo ago
lgs63042ep.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
lgs63042ep.step fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body regenerated from the footprint F.Fab outline) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'ESOP-8' denotes an exposed pad) · Ray 1mo ago
page.json lgs63042ep: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 20h ago
README.md lgs63042ep: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago

LGS63042EP

Legend Si · LED Drivers · ESOP-8

LGS63042EP from Legend Si, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No external component required. Datasheet recommends grounding the pin.
2 GND power_in Ground pin. Common return for the controller and switch. Also connects to the exposed thermal pad on the ESOP-8 package.
3 SW power_out Internal power switch node (drain of the integrated 350mΩ low-side MOSFET). Externally connected to the power inductor and Schottky diode. Absolute max SW-to-GND voltage is 60V; max switch current 3A.
4 SW power_out Internal power switch node (second SW pin, tied to pin 3). Provides additional current-handling capacity and heat sinking for the SW node.
5 VIN/OUT power_in Output voltage detection point or input voltage connection point. Connects the LED current sampling resistor Rsense to the CSN end. Acts as an input voltage detection point in buck circuits and as an output voltage connection point in boost and lift applications. Operating input range 3.0V-60V (abs max 60V).
6 CSN input LED current detection pin. Connect to external LED current sampling resistor Rsence. Output current is set by IOUT = (VOUT(VIN) − VCSN) / Rsence, with typical (VOUT − VCSN) = 0.2V. Absolute max voltage: VIN−6V to VIN+0.3V.
7 OVP input Overvoltage protection pin. Connect to the output through a resistor divider (R1 to VOUT, R2 to GND). OVP trip is typically 1.0V (recovery 0.9V); trip output voltage set by VOUT_OVP = (1 + R1/R2) × 1.0V. Absolute max OVP-to-GND voltage: 6V.
8 EN input Enable / dimming input. For LGS63042 (PWM variant) drive with a digital PWM signal at 100Hz-100kHz; duty cycle sets the average LED current per IOUT = (0.2 × D) / Rsence. Rising threshold 0.5V (typ), falling 0.35V (typ), 800kΩ internal pull-down. Absolute max EN-to-GND: 6V. Do not leave floating.

Key specifications

Parameter Value
Manufacturer Legend Si
Package ESOP-8
Category LED-drv
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • LGS63042EP
  • LGS63042EPB5

CAD (KiCad official)

  • Symbol: LGS63042EP
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)
  • 3D model files: lgs63042ep-etched.step / lgs63042ep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lgs63042ep.step / lgs63042ep.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
lgs63042ep.step 193 KB You want the bare part, or you mark your own boards.
lgs63042ep-etched.step 2.0 MB You want the part with LGS63042EP already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 494 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Legend Si datasheet (22 pp, sha256 13f24f98441db88d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF