LDK120M30R from STMicroelectronics, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN	power_in	Input voltage of the LDO. Operating range 1.9 V to 5.5 V; absolute max -0.3 V to 7 V. Requires a 1 uF ceramic input capacitor to ground.
2	GND	power_in	Common ground reference for the device. All voltages are referred to this pin.
3	EN	input	Enable pin (logic input). Low = shutdown (Iq < 1 uA), High = active. VIL max 0.4 V, VIH min 1.2 V; abs max -0.3 V to VIN+0.3 V; input current up to 100 nA.
4	BYP	passive	Bypass capacitor pin (fixed-output version) for noise reduction; typical 10 nF ceramic to GND lowers output noise to ~51 uVRMS (10 Hz to 100 kHz). Optional; if unused, leave floating with no routing. Abs max 2 V. On the adjustable version this pin becomes ADJ (feedback input, VADJ = 0.8 V typ.); on the D version it is internally not connected.
5	OUT	power_out	Regulated output voltage of the LDO. Fixed 3.0 V for LDK120M30R, up to 200 mA output current with typ. 100 mV dropout at 100 mA. Requires a 1 uF (up to 22 uF) ceramic output capacitor to GND.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SOT-23-5
Category	PMIC
Pins	5

Ordering variants

Same part, different packaging or reel option.

LDK120M30R
LDK120C30R
LDK120PU30R

CAD (KiCad official)

Symbol: LDK120M30R
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (24 pp, sha256 67483d91800bf19c, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF