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ld7792sgs
Public Unreviewedby Ray
Leadtrend Tech AC-DC Controllers and Regulators, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownLD7792SGS
Leadtrend Tech · AC-DC Controllers and Regulators · SOP-16
LD7792SGS from Leadtrend Tech, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply voltage pin. Recommended operating range 10 V to 29 V; UVLO(on)=18 V typ, UVLO(off)=8 V typ, VCC OVP=31.5 V typ, PDR=7 V typ. Bypass with a 22-100 uF capacitor. |
| 2 | GND | power_in | Ground return for the controller. All small-signal returns and current-sense resistors reference to this pin. |
| 3 | FBCOMP | input | Voltage feedback pin for the Flyback stage. Connect a photo-coupler to close the secondary-side regulation loop. Also used for OLP (VOLP=4.2 V typ), burst mode (start 0.8 V / stop 0.4 V), PFC on/off threshold and heavy-load trigger (2.9 V). Internally divided 1/5.5 into the PWM comparator; open-loop clamp 5.4 V typ. |
| 4 | FBAUX | input | Zero-current detection and over-voltage protection for the Flyback unit. Sensed via a resistor from the transformer auxiliary winding; ZCD trip 50 mV, OVP trigger current 300 uA (4-cycle debounce), upper clamp 2 V, lower clamp 0 V. |
| 5 | OTP | input | External over-temperature protection pin. Sources 80 uA typ through an external NTC to ground; turn-off trip 1.0 V typ (with 400-600 us debounce), turn-on 1.35 V typ. Auto-recovery when temperature falls. |
| 6 | PFCCOMP | output | Output of the PFC voltage-loop transconductance error amplifier (GM=80 umho typ). Connect a 0.1-2.2 uF compensation capacitor to GND. Upper clamp 5.2 V typ, minimum clamp 0.9 V; PFC burst mode stop threshold 1.0 V typ. |
| 7 | PFCONOFF | input | Threshold-voltage setting pin for PFC ON/OFF loading control (compared against FBCOMP). Sources 24.5 uA typ for the PFC-OFF threshold and 25.75 uA typ for the PFC-ON threshold; set the threshold with an external resistor to GND. |
| 8 | PFCAUX | input | Zero-current detection input for the PFC boost stage. Connect through a 10-51 kohm resistor to the PFC auxiliary winding (recommended current ~1 mA, max 1.5 mA). ZCD trip 0.2 V, upper clamp 4 V, ZCD time-out 50 us typ. |
| 9 | VOSENSE | input | PFC output voltage sense input. Regulation reference is 2.5 V; PFC OVP trip 2.63 V (0.13 V hysteresis). Sources 8 uA at low line (VHV<=210 V) for line-compensation, 0 uA at high line (>=230 V). Enable/disable thresholds 1.1/0.9 V; internal pull-down 6 Mohm typ. Recommended capacitor <=10 nF. |
| 10 | FBSENSE | input | Flyback current-sense input. Connect to the Flyback MOSFET source sense resistor to implement cycle-by-cycle peak-current limit at VOCQR=0.65 V typ (350 ns LEB, 80 ns delay). OCP high-line compensation adds 200 uA through an external ROCP (100-1k ohm) when FBCOMP>2.9 V. |
| 11 | PFCSENSE | input | PFC current-sense input. Connect to the PFC MOSFET source sense resistor for cycle-by-cycle current limit; trip threshold 0.52 V at low line, 0.40 V at high line (>=230 V) with 250 ns LEB. Sense resistor value also selects PWM vs QRM frequency reduction mode (<=220 ohm PWM, >=820 ohm QRM). |
| 12 | PFCDRIVER | output | Gate-drive output for the external PFC boost MOSFET. CMOS totem-pole with 500/-1000 mA drive; output clamped at 13 V typ (VCC=17 V), rise time 130 ns / fall time 45 ns into 3 nF. Absolute max -0.3 V to 20 V. |
| 13 | FBDRIVER | output | Gate-drive output for the external Flyback MOSFET. CMOS totem-pole with 500/-1000 mA drive; output clamped at 13 V typ (VCC=17 V), rise time 130 ns / fall time 45 ns into 3 nF. Absolute max -0.3 V to 20 V. |
| 14 | CT | passive | External timing capacitor pin. Sets OLP debounce time, PFC turn-off debounce time and Flyback soft-start period; e.g. CT=47 nF gives FB soft-start 10 ms, OLP debounce 64 ms, PFC turn-off debounce 1 s. |
| 15 | NC | unconnected | No internal connection. Leave floating or tie to GND per PCB practice. |
| 16 | HV | power_in | High-voltage startup and line-sensing pin. Connect to AC line/neutral (input side of bridge diode preferred) through a 10-50 kohm resistor to source the VCC start-up current (1.5 mA below PDR, 3 mA between PDR and UVLO(on)); shut off after UVLO(on) to eliminate startup loss. Also senses AC peak for brown-in (105 V typ) / brown-out (85 V typ), high/low line detection (230 V / 210 V typ) and X-cap discharge (3 mA). Absolute max 650 V; add a 10 kohm series resistor to limit negative-spike current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leadtrend Tech |
| Package | SOP-16 |
| Category | PMIC |
| Pins | 16 |
Ordering variants
LD7792SGS
CAD (KiCad official)
- Symbol:
LD7792SGS - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leadtrend Tech datasheet (None pp, sha256
8872b49f05b5a019, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).