component
ld7576gs
Public Unreviewedby Ray
Leadtrend Tech AC-DC Controllers and Regulators, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownLD7576GS
Leadtrend Tech · AC-DC Controllers and Regulators · SOP-8
LD7576GS from Leadtrend Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CT | input | Programs the low-frequency timer / OLP delay time via an external capacitor to GND (recommended 0.047 µF to 0.1 µF, X7R; ~45 mS delay at 0.047 µF, ~110 mS at 0.1 µF). Also serves as a latch-mode trigger: pulling this pin below 0.8 V latches the controller off until AC power is recycled. |
| 2 | COMP | input | Voltage feedback pin (analogous to UC384X COMP). Driven by an opto-coupler from the secondary-side TL431 to close the regulation loop. Requires ≥102 pF X7R ceramic cap; open-loop voltage ~5.6 V; green-mode threshold ~2.35 V; OLP trip level 5.0 V; pulling below 1.2 V disables the gate output. |
| 3 | CS | input | Current sense pin for the primary MOSFET current. Maximum input threshold 0.85 V (typ), 230 nS internal leading-edge blanking, ~1 MΩ input impedance, 100 nS delay to output. Absolute max -0.3 V to +7 V; an external R-C filter is recommended for high-power designs to suppress negative turn-on spikes. |
| 4 | GND | power_in | Device ground return for all internal circuitry and the gate driver. Should have a short, low-inductance layout back to the CT capacitor and CS sense resistor. |
| 5 | OUT | output | Gate drive output for the external power MOSFET. CMOS totem-pole buffer with typical 500 mA source/sink capability; typical rise/fall 50 nS / 30 nS into 1 nF; maximum duty-cycle 75%. Absolute max -0.3 V to Vcc+0.3 V; includes an internal anti-floating pull-low resistor. |
| 6 | VCC | power_in | Supply voltage for the controller. Recommended operating range 11 V to 25 V (absolute max 30 V); UVLO(on) 16 V typ, UVLO(off) 10 V typ; OVP trip 28 V typ. Bypass with 10 µF to 47 µF; startup current <100 µA while the HV pin charges this rail. |
| 7 | NC | unconnected | No-connect. Present on the SOP-8 / DIP-8 packages only (absent from the SOP-7 variant). Leave floating. |
| 8 | HV | input | High-voltage startup input; connect to the positive terminal of the bulk (rectified DC) capacitor through a recommended 40 kΩ current-limit resistor. Sources ~1 mA (typ) into Vcc during startup and shuts off once Vcc trips UVLO(on) to eliminate steady-state startup losses. Absolute max 600 V; off-state leakage <35 µA at 500 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leadtrend Tech |
| Package | SOP-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
LD7576GSLD7576GSJGSLD7576GSHGSLD7576GSKGSLD7576GSPSLD7576GSJPSLD7576GSHPSLD7576GSKPSLD7576GSPNLD7576GSJPNLD7576GSHPNLD7576GSKPNLD7576GSGRLD7576GSJGRLD7576GSHGRLD7576GSKGR
CAD (KiCad official)
- Symbol:
LD7576GS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leadtrend Tech datasheet (None pp, sha256
2d9941417fcbc06b, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).