LAN9252I from Microchip, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OSCI	input	External 25 MHz crystal input. Can also be driven single-ended by a clock oscillator (leave OSCO unconnected in that case).
2	OSCO	output	External 25 MHz crystal output.
3	OSCVDD12	power_in	Crystal oscillator +1.2V supply. Supplied by the on-chip regulator unless REG_EN configures regulator-off mode.
4	OSCVSS	power_in	Crystal oscillator ground.
5	VDD33	power_in	+3.3V supply for the internal regulators. Must be supplied even if internal regulators are disabled.
6	VDDCR	power_in	+1.2V digital core supply. Supplied by the on-chip regulator unless REG_EN configures regulator-off mode. Pin 6 needs 1 µF and 470 pF decoupling caps in parallel to ground.
7	REG_EN	input	Regulator enable. Tie to 3.3V to enable the internal 1.2V regulators; tie low to disable and supply VDDCR/OSCVDD12 externally.
8	FXLOSEN	input	Port A and B FX-LOS enable strap. 3-level input: <1V selects FX-SD / copper twisted pair, 1.5V selects FX-LOS on port A only, >2V selects FX-LOS on both ports.
9	FXSDA/FXLOSA/FXSDENA	bidirectional	Port A fiber signal-detect (FXSDA, LVPECL input, >2V typ = valid), fiber loss-of-signal (FXLOSA, Schmitt input with pull-up), or FX-SD enable strap (FXSDENA, analog input; >1V typ selects FX-SD). Function selected by FXLOSEN.
10	FXSDB/FXLOSB/FXSDENB	bidirectional	Port B fiber signal-detect (FXSDB, LVPECL input, >2V typ = valid), fiber loss-of-signal (FXLOSB, Schmitt input with pull-up), or FX-SD enable strap (FXSDENB, analog input; >1V typ selects FX-SD). Function selected by FXLOSEN.
11	RST#	bidirectional	Active-low system reset. Input from external hardware; also driven low by the device during POR or an EtherCAT reset command sequence. Internal pull-up; open-drain output.
12	D2/AD2/SOF/SIO2	bidirectional	Chip-mode muxed: HBI-Indexed data D2, HBI-Multiplexed AD2, Digital-I/O Start-of-Frame output SOF, or SPI/SQI SIO2.
13	D1/AD1/EOF/SO/SIO1	bidirectional	Chip-mode muxed: HBI D1, HBI AD1, Digital-I/O End-of-Frame output EOF, SPI serial data output SO, or SQI SIO1.
14	VDDIO	power_in	+1.8V to +3.3V variable I/O supply.
15	D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1	bidirectional	Chip-mode muxed: HBI D14, HBI AD14, Digital-I/O DIGIO8, SPI+GPIO GPI8/GPO8, or SPI+MII MII_TXD3 / TX_SHIFT1 strap.
16	D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0	bidirectional	Chip-mode muxed: HBI D13, HBI AD13, Digital-I/O DIGIO7, SPI+GPIO GPI7/GPO7, or SPI+MII MII_TXD2 / TX_SHIFT0 strap.
17	D0/AD0/WD_STATE/SI/SIO0	bidirectional	Chip-mode muxed: HBI D0, HBI AD0, Digital-I/O SyncManager Watchdog State output WD_STATE, SPI serial data input SI, or SQI SIO0.
18	SYNC1/LATCH1	bidirectional	Distributed-Clock Sync1 (output) or Latch1 (input). Direction is bitwise configurable. High-impedance until EEPROM is loaded.
19	D9/AD9/LATCH_IN/SCK	bidirectional	Chip-mode muxed: HBI D9, HBI AD9, Digital-I/O external data latch input LATCH_IN, or SPI/SQI serial clock SCK.
20	VDDIO	power_in	+1.8V to +3.3V variable I/O supply.
21	D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1	bidirectional	Chip-mode muxed: HBI D12, HBI AD12, Digital-I/O DIGIO6, SPI+GPIO GPI6/GPO6, or SPI+MII MII_TXD1.
22	D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0	bidirectional	Chip-mode muxed: HBI D11, HBI AD11, Digital-I/O DIGIO5, SPI+GPIO GPI5/GPO5, or SPI+MII MII_TXD0.
23	D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN	bidirectional	Chip-mode muxed: HBI D10, HBI AD10, Digital-I/O DIGIO4, SPI+GPIO GPI4/GPO4, or SPI+MII MII_TXEN.
24	VDDCR	power_in	+1.2V digital core supply (regulator output or external).
25	A1/ALELO/OE_EXT/MII_CLK25	bidirectional	Chip-mode muxed: HBI address bit A1, HBI Address-Latch-Enable Low ALELO, Digital-I/O Output-Enable OE_EXT (active low clears output data), or SPI+MII 25 MHz clock output MII_CLK25.
26	A3/DIGIO11/GPI11/GPO11/MII_RXDV	bidirectional	Chip-mode muxed: HBI address bit A3, Digital-I/O DIGIO11, SPI+GPIO GPI11/GPO11, or SPI+MII receive-data-valid MII_RXDV. No function in HBI-Multiplexed mode.
27	A4/DIGIO12/GPI12/GPO12/MII_RXD0	bidirectional	Chip-mode muxed: HBI address bit A4, Digital-I/O DIGIO12, SPI+GPIO GPI12/GPO12, or SPI+MII MII_RXD0.
28	CS/DIGIO13/GPI13/GPO13/MII_RXD1	bidirectional	Chip-mode muxed: HBI chip-select CS, Digital-I/O DIGIO13, SPI+GPIO GPI13/GPO13, or SPI+MII MII_RXD1.
29	A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL	bidirectional	Chip-mode muxed: HBI address bit A2, HBI Address-Latch-Enable High ALEHI, Digital-I/O DIGIO10, SPI+GPIO GPI10/GPO10, SPI+MII link/activity LED port 2 LINKACTLED2, or MII link-polarity strap MII_LINKPOL.
30	WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2	bidirectional	Chip-mode muxed: HBI write strobe WR / data-enable ENB, Digital-I/O DIGIO14, SPI+GPIO GPI14/GPO14, or SPI+MII MII_RXD2.
31	RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3	bidirectional	Chip-mode muxed: HBI read strobe RD / read-or-write RD_WR, Digital-I/O DIGIO15, SPI+GPIO GPI15/GPO15, or SPI+MII MII_RXD3.
32	VDDIO	power_in	+1.8V to +3.3V variable I/O supply.
33	A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER	bidirectional	Chip-mode muxed: HBI address bit A0 or upper data D15, HBI AD15, Digital-I/O DIGIO9, SPI+GPIO GPI9/GPO9, or SPI+MII receive-error MII_RXER.
34	SYNC0/LATCH0	bidirectional	Distributed-Clock Sync0 (output) or Latch0 (input). Direction is bitwise configurable. High-impedance until EEPROM is loaded.
35	D3/AD3/WD_TRIG/SIO3	bidirectional	Chip-mode muxed: HBI D3, HBI AD3, Digital-I/O SyncManager Watchdog Trigger output WD_TRIG, or SQI SIO3.
36	D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK	bidirectional	Chip-mode muxed: HBI D6, HBI AD6, Digital-I/O DIGIO0, SPI+GPIO GPI0/GPO0, or SPI+MII receive clock MII_RXCLK.
37	VDDIO	power_in	+1.8V to +3.3V variable I/O supply.
38	VDDCR	power_in	+1.2V digital core supply (regulator output or external).
39	D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC	bidirectional	Chip-mode muxed: HBI D7, HBI AD7, Digital-I/O DIGIO1, SPI+GPIO GPI1/GPO1, or SPI+MII SMI clock MII_MDC.
40	D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO	bidirectional	Chip-mode muxed: HBI D8, HBI AD8, Digital-I/O DIGIO2, SPI+GPIO GPI2/GPO2, or SPI+MII SMI data MII_MDIO (needs external pull-up).
41	TESTMODE	input	Test-mode input; must be tied to VSS for proper operation. Internal pull-down.
42	EESDA/TMS	bidirectional	Dual-function: EEPROM I2C serial data (open-drain, requires external pull-up) or JTAG test-mode-select TMS.
43	EESCL/TCK	bidirectional	Dual-function: EEPROM I2C serial clock (open-drain, requires external pull-up) or JTAG test-clock TCK.
44	IRQ	output	Interrupt request output. Polarity, source, and buffer type (push-pull or open-drain) are programmable via the Interrupt Configuration Register (IRQ_CFG).
45	RUNLED/E2PSIZE	bidirectional	Run-LED output (open-drain/open-source, controlled by AL Status Register) and EEPROM-size configuration strap (low = 1K-16K bit, high = 32K bit-4M bit).
46	LINKACTLED1/TDI/CHIP_MODE1	bidirectional	Port 1 Link/Activity LED output (open-drain/open-source), JTAG test-data-input TDI, or Chip-Mode configuration strap CHIP_MODE1.
47	VDDIO	power_in	+1.8V to +3.3V variable I/O supply.
48	LINKACTLED0/TDO/CHIP_MODE0	bidirectional	Port 0 Link/Activity LED output (open-drain/open-source), JTAG test-data-output TDO, or Chip-Mode configuration strap CHIP_MODE0.
49	D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK	bidirectional	Chip-mode muxed: HBI D4, HBI AD4, Digital-I/O DIGIO3, SPI+GPIO GPI3/GPO3, or SPI+MII link-status input MII_LINK.
50	D5/AD5/OUTVALID/SCS#	bidirectional	Chip-mode muxed: HBI D5, HBI AD5, Digital-I/O Output-Valid output OUTVALID, or SPI/SQI slave chip-select SCS# (active low, pull-up).
51	VDD33TXRX1	power_in	+3.3V analog supply for Port A PHY (or separate ~2.5V through magnetics).
52	TXNA	bidirectional	Port A twisted-pair TX/RX negative channel 1 (AIO). In fiber mode: Port A FX TX negative (OLVPECL output). MDIX may internally swap TX/RX.
53	TXPA	bidirectional	Port A twisted-pair TX/RX positive channel 1 (AIO). In fiber mode: Port A FX TX positive (OLVPECL output). MDIX may internally swap TX/RX.
54	RXNA	bidirectional	Port A twisted-pair TX/RX negative channel 2 (AIO). In fiber mode: Port A FX RX negative (analog input). MDIX may internally swap TX/RX.
55	RXPA	bidirectional	Port A twisted-pair TX/RX positive channel 2 (AIO). In fiber mode: Port A FX RX positive (analog input). MDIX may internally swap TX/RX.
56	VDD12TX1	power_in	+1.2V Port A transmitter supply. Must be tied to VDD12TX2. Supplied by on-chip regulator or an external 1.2V source.
57	RBIAS	passive	Bias reference. Connect through a 12.1 kΩ ±1% resistor to ground (nominal 1.2V, ~1 mW dissipation).
58	VDD33BIAS	power_in	+3.3V master-bias analog supply.
59	VDD12TX2	power_in	+1.2V Port B transmitter supply. Must be tied to VDD12TX1. Supplied by on-chip regulator or an external 1.2V source.
60	RXPB	bidirectional	Port B twisted-pair TX/RX positive channel 2 (AIO). In fiber mode: Port B FX RX positive (analog input). MDIX may internally swap TX/RX.
61	RXNB	bidirectional	Port B twisted-pair TX/RX negative channel 2 (AIO). In fiber mode: Port B FX RX negative (analog input). MDIX may internally swap TX/RX.
62	TXPB	bidirectional	Port B twisted-pair TX/RX positive channel 1 (AIO). In fiber mode: Port B FX TX positive (OLVPECL output). MDIX may internally swap TX/RX.
63	TXNB	bidirectional	Port B twisted-pair TX/RX negative channel 1 (AIO). In fiber mode: Port B FX TX negative (OLVPECL output). MDIX may internally swap TX/RX.
64	VDD33TXRX2	power_in	+3.3V analog supply for Port B PHY (or separate ~2.5V through magnetics).
EP	VSS	power_in	Exposed pad, common ground. Must be connected to the ground plane with a via array.

Key specifications

Parameter	Value
Manufacturer	Microchip
Package	QFN-64-EP(9x9)
Category	Interface
Pins	65

Ordering variants

Same part, different packaging or reel option.

LAN9252IML
LAN9252ITML
LAN9252IPT
LAN9252ITPT

CAD (KiCad official)

Symbol: LAN9252I
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`lan9252i.step`	359 KB	You want the bare part, or you mark your own boards.
`lan9252i-etched.step`	2.6 MB	You want the part with `LAN9252I` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 680 faces against 398 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip datasheet (329 pp, sha256 562783e8c3ae2843, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF