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lan8710ai-ezk-tr
Public Unreviewedby Ray
Microchip Buffer/Driver/Transceiver, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.
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README
markdownLAN8710AI-EZK-TR
Microchip · Buffer/Driver/Transceiver · QFN-32-EP(5x5)
LAN8710AI-EZK-TR from Microchip, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD2A | power_in | +3.3V analog port power for Channel 2 and the internal 1.2V regulator. Bypass per the reference schematic. |
| 2 | LED2/nINTSEL | bidirectional | Link speed LED2 output (active when 100 Mbps). At power-on reset the pin is sampled as the nINTSEL configuration strap that selects nINT vs TXER/TXD4 on pin 18: floated/pulled to VDD2A = nINT (default); pulled low to VSS = TXER/TXD4. |
| 3 | LED1/REGOFF | bidirectional | Link/activity LED1 output (active on valid link, blinks on activity). At POR the pin is sampled as REGOFF strap: pulled high to VDD2A disables the internal 1.2V regulator (external 1.2V must be supplied to VDDCR); floated or low leaves the regulator enabled (default). |
| 4 | XTAL2 | output | External 25 MHz crystal output. Leave unconnected when driving XTAL1/CLKIN from a single-ended clock oscillator. |
| 5 | XTAL1/CLKIN | input | External 25 MHz crystal input, or single-ended clock oscillator input (CLKIN). Provides the device reference clock. |
| 6 | VDDCR | power_in | +1.2V digital core supply. Normally driven by the on-chip regulator; must be supplied externally when REGOFF strap disables the regulator. Decouple with 1 uF and 470 pF in parallel to VSS. |
| 7 | RXCLK/PHYAD1 | output | MII receive clock output: 25 MHz in 100BASE-TX, 2.5 MHz in 10BASE-T. Not used in RMII mode. At POR the pin is sampled as PHYAD1 strap (combined with PHYAD0/PHYAD2 to set the SMI address). |
| 8 | RXD3/PHYAD2 | output | MII receive data bit 3 (used in MII mode only; unused in RMII). At POR the pin is sampled as PHYAD2 strap (combined with PHYAD0/PHYAD1 to set the SMI address). |
| 9 | RXD2/RMIISEL | output | MII receive data bit 2 (MII mode only; unused in RMII). At POR the pin is sampled as RMIISEL strap: low to VSS selects MII mode, high to VDDIO selects RMII mode. |
| 10 | RXD1/MODE1 | output | Receive data bit 1 on the MII/RMII receive path. At POR the pin is sampled as MODE1 strap (combined with MODE0/MODE2 to set the default PHY operating mode). |
| 11 | RXD0/MODE0 | output | Receive data bit 0 on the MII/RMII receive path. At POR the pin is sampled as MODE0 strap (combined with MODE1/MODE2 to set the default PHY operating mode). |
| 12 | VDDIO | power_in | Variable I/O supply from +1.6V to +3.6V. Sets the logic level of all VIS/VO8 digital I/Os. |
| 13 | RXER/RXD4/PHYAD0 | output | Receive Error output (RXER), optional in RMII. When configured for Symbol (5B decoding) interface, functions as RXD4 (MSB of received 5-bit symbol). At POR the pin is sampled as PHYAD0 strap (with PHYAD1/PHYAD2 to set the SMI address). |
| 14 | CRS | output | MII carrier sense output. Indicates detection of a carrier in MII mode. |
| 15 | COL/CRS_DV/MODE2 | output | In MII mode: COL collision detect output. In RMII mode: CRS_DV combined carrier-sense/receive-data-valid output. At POR the pin is sampled as MODE2 strap (with MODE0/MODE1 to set the default PHY operating mode). |
| 16 | MDIO | bidirectional | Serial Management Interface (SMI) data input/output. Requires external pull-up to VDDIO (open-drain output type VOD8). |
| 17 | MDC | input | Serial Management Interface (SMI) clock input from the MAC/host controller. |
| 18 | nINT/TXER/TXD4 | bidirectional | Function selected by the nINTSEL strap (pin 2). Default: active-low interrupt output nINT (open-drain style; requires external pull-up to VDDIO). Alternate: TXER input (asserts /H/ error code in 4B/5B encode; ignored in 10BASE-T) or TXD4 (MII 5-bit symbol MSB). Not used in RMII. |
| 19 | nRST | input | Active-low external system reset input (Schmitt-triggered, internal 50 uA pull-up). |
| 20 | TXCLK | output | MII transmit clock output used by the MAC to latch data into the transceiver: 25 MHz in 100BASE-TX, 2.5 MHz in 10BASE-T. Not used in RMII mode. |
| 21 | TXEN | input | Transmit enable input from the MAC. Indicates valid transmit data on TXD[3:0] (MII) or TXD[1:0] (RMII). Internal 50 uA pull-down. |
| 22 | TXD0 | input | Transmit data bit 0 from the MAC (all modes). |
| 23 | TXD1 | input | Transmit data bit 1 from the MAC (all modes). |
| 24 | TXD2 | input | Transmit data bit 2 from the MAC (MII mode). Must be tied to GND in RMII mode. |
| 25 | TXD3 | input | Transmit data bit 3 from the MAC (MII mode). Must be tied to GND in RMII mode. |
| 26 | RXDV | output | Receive data valid output. Indicates that recovered/decoded data is available on the RXD pins (MII). |
| 27 | VDD1A | power_in | +3.3V analog port power for Channel 1 (transmit/receive analog front-end). |
| 28 | TXN | bidirectional | Ethernet Channel 1 negative differential I/O (AIO). Connects through magnetics to the RJ45. |
| 29 | TXP | bidirectional | Ethernet Channel 1 positive differential I/O (AIO). Connects through magnetics to the RJ45. |
| 30 | RXN | bidirectional | Ethernet Channel 2 negative differential I/O (AIO). Connects through magnetics to the RJ45. |
| 31 | RXP | bidirectional | Ethernet Channel 2 positive differential I/O (AIO). Connects through magnetics to the RJ45. |
| 32 | RBIAS | passive | Analog bias reference. Connect a 12.1 kΩ 1% resistor from this pin to VSS; nominal pin voltage 1.2V, dissipation ~1 mW. |
| 33 | VSS | power_in | Exposed thermal/ground pad on the bottom of the QFN package. Must be connected to the PCB ground plane with a via array for both electrical ground and thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip |
| Package | QFN-32-EP(5x5) |
| Category | Logic |
| Pins | 33 |
Ordering variants
LAN8710AI-EZK-TRLAN8710AI-EZK-TREZCLAN8710AI-EZK-TRABC
CAD (KiCad official)
- Symbol:
LAN8710AI-EZK-TR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip datasheet (None pp, sha256
0f4b8670bcfc7e63, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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