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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

LAN7500I-ABZJ

Microchip Tech · Ethernet Controllers · QFN-56-EP(8x8)

LAN7500I-ABZJ from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TDI	input	JTAG (IEEE 1149.1) test data input. Buffer VIS with 50 uA internal pull-up. Tie to VDDVARIO when unused.
2	TCK	input	JTAG (IEEE 1149.1) test clock. Buffer VIS with 50 uA internal pull-down. Tie to VSS when unused.
3	TMS	input	JTAG (IEEE 1149.1) test mode select. Buffer VIS with 50 uA internal pull-up. Tie to VDDVARIO when unused.
4	TDO	output	JTAG (IEEE 1149.1) test data output. Buffer VO8 (variable-voltage 8 mA push-pull).
5	XI	input	External 25 MHz crystal input (ICLK). May also be driven by a single-ended clock oscillator; in that case leave XO unconnected.
6	XO	output	External 25 MHz crystal output (OCLK). Leave unconnected when XI is driven by a single-ended oscillator.
7	VDDVARIO	power_in	+3.3 V / +2.5 V variable I/O power supply input. Sets the digital I/O rail voltage; four VDDVARIO pins on the package.
8	VDD12CORE	power_in	+1.2 V digital core power supply input. Six VDD12CORE pins on the package.
9	SW_MODE	output	Switching regulator mode control output (VO6, 6 mA). When asserted, places the external switching regulator into power-saving mode. Polarity/assertion controlled by SW_MODE_POL and SW_MODE_SEL bits of Configuration Flags 1.
10	GPIO7	bidirectional	General-purpose I/O 7. Programmable as push-pull, open-drain, or Schmitt-triggered input. Buffer VIS/VO8/VOD8 with 50 uA internal pull-up.
11	VDD12CORE	power_in	+1.2 V digital core power supply input.
12	USBDM	bidirectional	USB D- analog bidirectional (AIO). Functionality may be swapped with USBDP via the Port Swap bit of Configuration Flags 0.
13	USBDP	bidirectional	USB D+ analog bidirectional (AIO). Functionality may be swapped with USBDM via the Port Swap bit of Configuration Flags 0.
14	VBUS_DET	input	Upstream VBUS power detect input (IS_5V, 5 V tolerant Schmitt input with internal pull-down). For bus-powered operation, tie to VDD33A. For self-powered operation, refer to reference schematics.
15	VDD33A	power_in	+3.3 V analog power supply input.
16	USBRBIAS	passive	External USB bias resistor (AI). Sets HS transmit current level and on-chip termination impedance. Connect an external 12 kOhm 1% resistor to ground.
17	VDD12USBPLL	power_in	+1.2 V USB PLL power supply input.
18	GPIO8	bidirectional	General-purpose I/O 8. Programmable as push-pull, open-drain, or Schmitt-triggered input. Buffer VIS/VO6/VOD6 with 50 uA internal pull-up (6 mA drive rather than the usual 8 mA).
19	VDDVARIO	power_in	+3.3 V / +2.5 V variable I/O power supply input.
20	VDD12CORE	power_in	+1.2 V digital core power supply input.
21	GPIO9	bidirectional	General-purpose I/O 9. Programmable as push-pull, open-drain, or Schmitt-triggered input. Buffer VIS/VO8/VOD8 with 50 uA internal pull-up.
22	GPIO10	bidirectional	General-purpose I/O 10. Programmable as push-pull, open-drain, or Schmitt-triggered input. Buffer VIS/VO8/VOD8 with 50 uA internal pull-up.
23	VDD12CORE	power_in	+1.2 V digital core power supply input.
24	VDDVARIO	power_in	+3.3 V / +2.5 V variable I/O power supply input.
25	GPIO11	bidirectional	General-purpose I/O 11. Programmable as push-pull, open-drain, or Schmitt-triggered input. Buffer VIS/VO8/VOD8 with 50 uA internal pull-up.
26	EECLK	output	EEPROM clock output to the external MicroWire EEPROM (VO8).
27	EEDI	input	EEPROM data in. Driven by the EEDO output of the external EEPROM. Buffer VIS with internal pull-down.
28	EEDO	output	EEPROM data out. Drives the EEDI input of the external EEPROM (VO8).
29	EECS	output	EEPROM chip select (VO8). May tri-state briefly during power-up; an external pull-down is recommended to prevent false selection.
30	VDD12CORE	power_in	+1.2 V digital core power supply input.
31	GPIO0/LED0	bidirectional	Muxed pin: GPIO0 (VIS/VO8/VOD8 with pull-up) or Indicator LED0 (VOD8, open-drain LED driver). Default at reset is GPIO. Used with LED1 to indicate Link/Speed or Link/Speed/Activity.
32	GPIO1/LED1	bidirectional	Muxed pin: GPIO1 or Indicator LED1. LED1 combines with LED0 to indicate Ethernet Link/Speed or Link/Speed/Activity. Default: GPIO.
33	GPIO2/LED2	bidirectional	Muxed pin: GPIO2 or Indicator LED2 (Ethernet Link and Activity, or Activity only). Default: GPIO.
34	GPIO3/LED3	bidirectional	Muxed pin: GPIO3 or Indicator LED3 (Ethernet Link indicator). Default: GPIO.
35	GPIO4/LED4	bidirectional	Muxed pin: GPIO4 or Indicator LED4 (Ethernet Full-Duplex indicator). Default: GPIO.
36	VDD12CORE	power_in	+1.2 V digital core power supply input.
37	VDDVARIO	power_in	+3.3 V / +2.5 V variable I/O power supply input.
38	GPIO5/PME	bidirectional	Muxed pin: GPIO5 (VIS/VO8/VOD8 with pull-up) or PME output (VO8/VOD8). When PME mode of operation is in effect this pin signals Power Management Event.
39	TEST	input	Test pin. Must always be connected to VSS for proper operation.
40	GPIO6/PME_MODE_SEL	bidirectional	Muxed pin: GPIO6 (VIS/VO8/VOD8 with pull-up) or PME_MODE_SEL input (VIS with pull-up) when PME mode is in effect.
41	ETHRBIAS	passive	External PHY bias resistor (AI). Used for internal bias circuits. Connect to an external 8.06 kOhm 1% resistor to ground.
42	nRESET/PME_CLEAR	input	Muxed pin: active-low system reset (nRESET, VIS with pull-up) allowing external hardware to reset the device, or PME_CLEAR input when PME mode is in effect. Assertion of nRESET is required following power-on.
43	TR0N	bidirectional	Ethernet TX/RX negative channel 0 (AIO). Connects to the negative side of magnetics pair 0 for 10/100/1000BASE-T.
44	TR0P	bidirectional	Ethernet TX/RX positive channel 0 (AIO). Connects to the positive side of magnetics pair 0 for 10/100/1000BASE-T.
45	VDD12A	power_in	+1.2 V Ethernet analog port power supply input (channels 0-3). Four VDD12A pins on the package.
46	TR1N	bidirectional	Ethernet TX/RX negative channel 1 (AIO).
47	TR1P	bidirectional	Ethernet TX/RX positive channel 1 (AIO).
48	VDD12A	power_in	+1.2 V Ethernet analog port power supply input.
49	VDD12BIAS	power_in	+1.2 V Ethernet bias power supply input.
50	VDD12PLL	power_in	+1.2 V Ethernet PLL power supply input.
51	TR2N	bidirectional	Ethernet TX/RX negative channel 2 (AIO).
52	TR2P	bidirectional	Ethernet TX/RX positive channel 2 (AIO).
53	VDD12A	power_in	+1.2 V Ethernet analog port power supply input.
54	TR3N	bidirectional	Ethernet TX/RX negative channel 3 (AIO).
55	TR3P	bidirectional	Ethernet TX/RX positive channel 3 (AIO).
56	VDD12A	power_in	+1.2 V Ethernet analog port power supply input.
57	VSS	power_in	Exposed pad on bottom of package. Common ground; must be connected to ground.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-56-EP(8x8)
Category	Interface
Pins	57

Ordering variants

Same part, different packaging or reel option.

LAN7500I-ABZJ

CAD (KiCad official)

Symbol: LAN7500I-ABZJ
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (56 pp, sha256 a786a4302ef5dbd6, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF