L7987TR from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBIAS	power_in	Auxiliary input to supply part of the analog circuitry to increase efficiency at light load. Typically tied to the regulated output voltage or an external rail higher than 3 V; connect to signal GND (or bypass with a 1 uF ceramic) if unused.
2	VIN	power_in	DC input voltage (4.5 V to 61 V operating range). Tie both VIN pins together at the package.
3	VIN	power_in	DC input voltage (4.5 V to 61 V operating range). Tie both VIN pins together at the package.
4	VCC	power_in	Filtered DC input voltage to the internal circuitry. Bypass to signal GND with a 1 uF ceramic capacitor.
5	EN	input	Active-high enable pin (device OFF <= 0.30 V, ON >= 0.35 V). Connect to VCC if not used.
6	SS	passive	Soft-start pin. An internal 5 uA typ. current source charges an external capacitor from this pin to set the soft-start time.
7	SYNCH	bidirectional	Master/slave synchronization pin. Sources a pulse when configured as master and accepts an external sync input (>=280 kHz) when configured as slave; up to 5 slave devices can share this line.
8	COMP	output	Error-amplifier output. Compensation network (Type II or Type III) is connected between COMP and FB/GND to shape the loop response.
9	FB	input	Inverting input of the error amplifier (VFB = 0.8 V typ.). Connect to the output resistor divider to set the regulated output voltage.
10	FSW	passive	Switching-frequency programming pin. A pull-down resistor to GND selects the switching frequency (250 kHz - 1.5 MHz); leaving FSW floating sets ~250 kHz.
11	ILIM	passive	Peak-current-limit programming pin. A pull-down resistor to GND selects the inductor peak current limit; floating ILIM yields the default ~4.0 A limit.
12	PGOOD	output	Open-collector power-good output. Pulled low when the FB voltage is out of regulation (rising threshold 0.70 V typ., 30 mV hysteresis); requires an external pull-up.
13	LX	power_out	Switching node (output of the internal high-side n-DMOS). Tie both LX pins together and connect to the external inductor and freewheeling diode.
14	LX	power_out	Switching node (output of the internal high-side n-DMOS). Tie both LX pins together and connect to the external inductor and freewheeling diode.
15	BOOT	passive	Bootstrap pin for the high-side gate drive. Connect a 100 nF ceramic capacitor (typ.) between BOOT and LX; the internal regulator refreshes the boot capacitor during the off-time.
16	GND	power_in	Signal ground reference for the internal analog circuitry.
17	EP	power_in	Exposed thermal pad on package underside. Must be connected to signal GND and to a large copper area for heat dissipation (RthJA = 40 C/W on demo board).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-16-EP
Category	PMIC
Pins	17

Ordering variants

Same part, different packaging or reel option.

L7987TR

CAD (KiCad official)

Symbol: L7987TR
Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-16-EP (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (37 pp, sha256 9ea1c120a6bc8ac2, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF