L6564TDTR from STMicroelectronics, in a SSOP-10-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INV	input	Inverting input of the internal error amplifier. Output voltage of the PFC pre-regulator is fed into this pin through a resistor divider. High-impedance input; internal reference is 2.5 V (typ).
2	COMP	output	Error amplifier output. A compensation network between this pin and INV sets the voltage loop stability. Gate driver is inhibited (burst-mode) when VCOMP falls below ~2.4 V.
3	MULT	input	Main input to the multiplier. Connected to the rectified mains voltage via a resistor divider to provide the sinusoidal reference for the current loop and to derive RMS mains information. Linear range 0-3 V; internal clamp ~9.5 V.
4	CS	input	PWM comparator current-sense input. MOSFET current is sensed through a shunt and applied here; compared to an internal reference to terminate the on-time. A second 1.7 V comparator detects abnormal currents (inductor saturation) and triggers a safety hiccup.
5	VFF	input	Voltage feedforward input to the multiplier for the 1/V^2 function. A capacitor and parallel resistor (100 kΩ min to 2 MΩ max) from this pin to GND complete the peak-holding circuit that derives RMS mains information. Also feeds the brownout comparator: <0.8 V shuts down the IC (not latched); restart above 0.88 V.
6	PFC_OK	input	PFC pre-regulator output-voltage monitoring / disable input. Senses PFC output through a resistor divider. Above 2.5 V the IC stops switching (OVP); if simultaneously VINV<1.66 V a feedback failure is latched off. Below 0.23 V the IC is shut down; restart above 0.27 V (usable as remote on/off).
7	ZCD	input	Boost-inductor demagnetization sensing input for transition-mode operation. A negative-going edge triggers MOSFET turn-on. Max ZCD current -10 mA (source) / 10 mA (sink).
8	GND	power_in	Ground. Common current return for both the signal part of the IC and the gate driver.
9	GD	output	Gate driver output. Totem-pole stage capable of 600 mA source / 800 mA sink for MOSFET or IGBT drive. High-level clamped at ~12 V to prevent excessive gate voltages; active pull-down during UVLO.
10	Vcc	power_in	Supply voltage for both the signal part of the IC and the gate driver. Operating range 10.3-22.5 V after turn-on; turn-on threshold ~12 V, turn-off ~9.5 V, internal Zener clamp ~25 V. A ~0.1 µF bypass to GND is recommended.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SSOP-10-150mil
Category	PMIC
Pins	10

Ordering variants

Same part, different packaging or reel option.

L6564TDTR

CAD (KiCad official)

Symbol: L6564TDTR
Footprint: Package_SO:SSOP-10_3.9x4.9mm_P1.00mm
3D model: SSOP-10-150mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (33 pp, sha256 d9194e06a2a0df36, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF