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l4981ad013tr

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STMicroelectronics AC-DC Controllers and Regulators, SOIC-20-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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L4981AD013TR

STMicroelectronics · AC-DC Controllers and Regulators · SOIC-20-300mil

L4981AD013TR from STMicroelectronics, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P-GND power_in Power ground return for the high-current gate-driver output stage. Should be tied to the source of the boost MOSFET and, via a low-impedance star point, back to signal ground (pin 10).
2 IPK input Peak current limit sense input. On L4981A a single resistor between pin 2 and the current-sense resistor sets the peak-current threshold; a second resistor to VREF (pin 11) can be added for improved precision. Absolute max -0.3 to 5.5 V (-2 V for t<=1us).
3 OVP input Overvoltage protection input. An external resistor divider from the boost output is compared against an internal 5.1 V (typ) reference to clamp the peak output voltage. Absolute max -0.3 to 9 V.
4 IAC input AC current input. A current proportional to the rectified mains voltage (typically injected through a high-value resistor from the rectified line) is fed into the internal multiplier to generate the current reference. Absolute max input current 5 mA.
5 CA-OUT output Current amplifier output. An external RC compensation network from this pin to ISENSE (pin 9) sets the current-loop gain and bandwidth. Sink/source ~=20 mA, output range approx. -0.3 to 8.5 V.
6 LFF input Load feed-forward input. Modulates the multiplier output current in proportion to load for faster transient response; best control between 1.5 V and 5.3 V. If unused, tie to VREF (pin 11). Absolute max -0.3 to 9 V.
7 VRMS input RMS line-voltage feed-forward input. An external RC low-pass filter from the rectified line produces a DC voltage proportional to line RMS, compensating for input line variations. Recommended operating range 1.5 V to 5.5 V; if unused, tie to VREF (pin 11). Absolute max -0.3 to 9 V.
8 MULT-OUT output Multiplier output / current amplifier non-inverting input. High-impedance node; must not be pulled below -0.5 V. Absolute max -0.5 to 7 V.
9 ISENSE input Current amplifier inverting input, connected to the boost inductor current-sense resistor through an input resistor. High-impedance node; do not allow the pin to fall below -0.5 V. Absolute max -0.5 to 7 V.
10 S-GND power_in Signal (analog) ground. Return for the reference, error/current amplifiers, oscillator, and protection comparators. Kelvin-connect to P-GND (pin 1) at a single star point.
11 VREF power_out Buffered internal voltage reference output, 5.1 V typ, +/-2% (4.97 to 5.23 V over -25 degC to 85 degC). Internally current-limited, can source up to 10 mA to bias external circuitry (LFF, VRMS, IPK divider, etc.).
12 SS output Soft-start pin. An external capacitor to ground is charged by an internal 100 uA (typ) current source, ramping the reference to the error amplifier and setting the soft-start time. Internally discharged during UVLO or overvoltage. Absolute max -0.3 to 9 V.
13 VA-OUT output Voltage-loop error amplifier output. An external RC network sets the voltage-loop compensation. Output swing typically 0.4 V (low) to ~=6.5 V (high); source/sink capability 2-20 mA. Absolute max -0.3 to 8.5 V.
14 VFEED input Voltage error amplifier inverting input, driven by a resistive divider from the boost output to set the regulated DC bus voltage. Internally referenced to VREF (5.1 V). Absolute max -0.3 to 9 V.
15 P-UVLO input Programmable under-voltage lockout threshold input. A resistor divider from VCC (or the bootstrap supply) programs the turn-on threshold with hysteresis. Absolute max -0.3 to 7 V.
16 SYNC bidirectional L4981A synchronization I/O (CMOS logic compatible). As SYNC-in, a rectangular clock applied at this pin synchronizes the internal oscillator (VIH >= 3.5 V, VIL <= 0.9 V, pulse width >= 800 ns). As SYNC-out, the internal oscillator emits a ~=0.3-0.8 us wide clock pulse to synchronize other devices. Absolute max -0.3 to 7 V.
17 ROSC passive Oscillator timing resistor. An external resistor to ground (typ 24 kOhm) sets the constant charging current for COSC. Absolute max -0.3 to 3 V.
18 COSC passive Oscillator timing capacitor. An external capacitor to ground (typ 1 nF with ROSC = 24 kOhm gives ~=100 kHz) sets the switching frequency. Peak-charge current ~=0.55 mA, discharge ~=11.5 mA. Absolute max -0.3 to 7 V, sink 15 mA.
19 VCC power_in Chip supply input (self-limited to <= 50 mA). Typical operating range up to 19.5 V; the device features low start-up current (0.3 mA typ) so it can be bootstrapped from the rectified mains through a resistor and held up by an auxiliary winding.
20 GDRV output Gate driver output. Bipolar-plus-DMOS totem-pole stage delivering >1 A source and up to 2 A sink peak (t = 1 us) to drive the boost power MOSFET or IGBT. Peak gate-drive voltage -1 V min (t = 0.1 us).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-20-300mil
Category PMIC
Pins 20

Ordering variants

  • L4981AD013TR
  • L4981AD013TRL4981BD
  • L4981AD013TRL4981B

CAD (KiCad official)

  • Symbol: L4981AD013TR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (None pp, sha256 607996fde19865e3, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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