Overview Files Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

KSZ8851SNLI-TR

Microchip · Ethernet Controllers · QFN-32(5x5)

KSZ8851SNLI-TR from Microchip, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LED0	output	Programmable LED0 output (open-drain-style, active LOW = LED on). Default indicates Link/Activity per CGCR[9].
2	PME	output	Power Management Event output (default active low, polarity set in PMECR). Asserted when a Wake-on-LAN event is detected, requesting host wake from low-power mode.
3	INTRN	output	Interrupt Not - active-low interrupt output to host CPU when any enabled interrupt status bit is set. Requires an external 4.7 kΩ pull-up resistor.
4	DGND	power_in	Digital IO ground.
5	VDD_CO1.8	power_out	1.8V on-chip LDO regulator output. Feeds VDD_A1.8 (pin 9) and VDD_D1.8 (pin 23) for core supply. Leave floating if VDD_IO = 1.8V (core is then sourced from the external 1.8V rail).
6	EED_IO	bidirectional	EEPROM serial data (in/out) to external configuration EEPROM. Also a strap-in at reset: pull-up = EEPROM present, floating/pull-down = no EEPROM (default). Latched into CCR bit 9.
7	EESK	output	EEPROM serial clock output to external EEPROM. Period is 4 µs (OBCR[1:0]=11 @25MHz) or 800 ns (OBCR[1:0]=00 @125MHz).
8	AGND	power_in	Analog ground.
9	VDD_A1.8	power_in	1.8V analog supply. Normally tied to VDD_CO1.8 (pin 5) through appropriate filtering; if VDD_IO=1.8V, source from the same external 1.8V rail as VDD_IO.
10	EECS	output	EEPROM chip-select output to external EEPROM.
11	RXP	bidirectional	10/100 Ethernet media-dependent interface, positive side. Physical receive (MDI) or transmit (MDIX) - polarity assigned by Auto MDI-X.
12	RXM	bidirectional	10/100 Ethernet media-dependent interface, negative side. Physical receive (MDI) or transmit (MDIX) - polarity assigned by Auto MDI-X.
13	AGND	power_in	Analog ground.
14	TXP	bidirectional	10/100 Ethernet media-dependent interface, positive side. Physical transmit (MDI) or receive (MDIX) - polarity assigned by Auto MDI-X.
15	TXM	bidirectional	10/100 Ethernet media-dependent interface, negative side. Physical transmit (MDI) or receive (MDIX) - polarity assigned by Auto MDI-X.
16	VDD_A3.3	power_in	3.3V analog VDD input supply for the PHY. Requires decoupling capacitors.
17	ISET	passive	PHY transmit bias current set. Connect a 3.01 kΩ 1% resistor from this pin to ground.
18	AGND	power_in	Analog ground.
19	RSTN	input	Hardware reset, active-low. Must be held low for a minimum of 10 ms after the 3.3V supply is stable.
20	X1	input	25 MHz crystal / oscillator input. Connect a 25 MHz crystal between X1 and X2, or drive X1 from a 3.3V-tolerant oscillator (leave X2 unconnected in that case). Clock accuracy ±50 ppm.
21	X2	output	25 MHz crystal feedback output. Connects to the other terminal of the 25 MHz crystal at X1; leave NC when using an external oscillator on X1.
22	DGND	power_in	Digital IO ground.
23	VDD_D1.8	power_in	1.8V digital core supply. Normally tied to VDD_CO1.8 (pin 5) through appropriate filtering; if VDD_IO=1.8V, source from the same external 1.8V rail as VDD_IO.
24	DGND	power_in	Digital IO ground.
25	VDD_IO	power_in	Digital IO supply - accepts 3.3V, 2.5V, or 1.8V. Requires decoupling capacitors.
26	CSN	input	SPI slave chip-select input, active low.
27	SO	tri_state	SPI slave serial data out (MISO). Tri-stated when CSN is negated - requires an external 4.7 kΩ pull-up to keep the line high while the driver is tri-stated.
28	SCLK	input	SPI slave serial clock input. Supports clock speeds up to 40 MHz.
29	DGND	power_in	Digital IO ground.
30	VDD_IO	power_in	Digital IO supply - accepts 3.3V, 2.5V, or 1.8V. Requires decoupling capacitors.
31	SI	input	SPI slave serial data in (MOSI).
32	LED1	output	Programmable LED1 output (active LOW = LED on). Default indicates 100BASE-T activity per CGCR[9]; see LED0 (pin 1).
33	EP	power_in	Exposed thermal pad on bottom of QFN. Datasheet labels it 'Paddle Ground on Bottom of Chip' - connect to ground plane for electrical/thermal grounding.

Key specifications

Parameter	Value
Manufacturer	Microchip
Package	QFN-32(5x5)
Category	Interface
Pins	33

Ordering variants

KSZ8851SNLI-TR
KSZ8851SNLI-TRKSZ8851SNL-TR

CAD (KiCad official)

Symbol: KSZ8851SNLI-TR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip datasheet (None pp, sha256 aa3a99d09769cc45, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

Open full view ↗

PCB Footprint