component
JTD4054
Public Unreviewedby Ray
JTD Battery Management, SOT-23-5L. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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markdownJTD4054
JTD · Battery Management · SOT-23-5L
JTD4054 from JTD, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CHRG | output | Open-drain charge-status indicator. Pulled low internally while charging; high-impedance when charging ends. Blinks (via internal switch toggling) if a charger is plugged in with no battery attached. VOL = 50 mV typ at ICHRG = 5 mA; leave floating or tied to GND if unused. |
| 2 | GND | power_in | Device ground / power return. |
| 3 | BAT | power_out | Battery positive terminal. Sources charge current to the Li-ion/Li-poly cell and regulates the float voltage to 4.2 V. Leakage into this pin drops to ~5 nA in sleep mode (VCC absent) and ~1.2 µA in standby. Absolute rating: -11 V to +13 V; max continuous current 500 mA. |
| 4 | VCC | power_in | Charger input supply, 4.5 V to 6.5 V typical (abs max 10 V). Charging starts when VCC exceeds the UVLO threshold (3.5 V typ) AND is at least ~110 mV above VBAT; the device enters low-power sleep when VCC falls below UVLO or within 50 mV of VBAT. Bypass with 2.2 µF to GND. |
| 5 | PROG | input | Charge-current program pin. A resistor RPROG from PROG to GND sets constant-current charge current: IBAT = 1000 V / RPROG (RPROG ≥ 2 kΩ, i.e. ICC ≤ 500 mA). Pin is regulated to 1.0 V in CC mode and to 0.1 V during trickle charge; end-of-charge is detected when this pin drops below 100 mV (15% of set current) for > 1.4 ms. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JTD |
| Package | SOT-23-5L |
| Category | PMIC |
| Pins | 5 |
CAD (KiCad official)
- Symbol:
JTD4054 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5L (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
jtd4054.step |
85 KB | You want the bare part, or you mark your own boards. |
jtd4054-etched.step |
1.3 MB | You want the part with JTD4054 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 332 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JTD datasheet (8 pp, sha256
c73d518dd59f6707, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).