JL7016M8 from JieLi Tech, in a QFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVSS	power_in	Audio analog ground return for the audio codec and DAC/ADC front-end. Tie to the system ground plane close to VCM/DACLP/DACRP.
2	NC	unconnected	No connect. Leave floating or tie to ground per JieLi reference design.
3	HPVDD/IOVDD	power_in	Dual-function pin: HPVDD is the audio (headphone) power input (V_HPVDD max +3 V) and IOVDD is the built-in linear voltage regulator output (typ 3.0 V, up to 200 mA) that also powers the digital IO rail (2.2 V-3.6 V). Decouple externally.
4	PG8	bidirectional	General purpose I/O port G bit 8. Alt-functions: MICIN2 (MIC2 single-ended input), MIC2_P (differential MIC2 positive), AMUX_C0 (analog mux channel C0).
5	PG7	bidirectional	General purpose I/O port G bit 7. Alt-functions: MIC_BIAS2 (built-in resistor bias for MIC2), MIC2_N (differential MIC2 negative), AMUX_C1, ADC15 (10-bit ADC channel 15).
6	PG5	bidirectional	General purpose I/O port G bit 5. Alt-functions: MIC_BIAS3, MIC3_N, AMUX_D1, ADC14, TMR3CK (Timer3 PWM clock input).
7	PGND	power_in	Power ground for the internal buck DC-DC converter. Route as a dedicated low-impedance return to the buck inductor / VBAT decoupling.
8	SW	power_out	Switching node of the on-chip buck DC-DC converter. Connect to the external buck inductor toward DCVDD (typ 1.25 V, up to 180 mA in DCDC mode).
9	VBAT	power_in	Lithium battery / main supply input (operating 2.2 V-4.4 V, abs max 4.5 V). Feeds the internal charger, LDO, and buck DC-DC.
10	VPWR/PP0	power_in	Charger power input (4.5-5.5 V, abs max 6 V) for the built-in Li-ion charger. Also a high-voltage-resistant GPIO (PP0) with alt-functions UART0 TXB/RXB, PWM3, CAP1.
11	DCVDD	power_in	Internal digital core power rail (typ 1.25 V). Fed from the SW pin through the external buck inductor; requires bulk decoupling capacitor.
12	PB3	bidirectional	High-voltage-resistant GPIO port B bit 3 (V_IH up to +5 V). Alt-functions: SPI4 Data Out (A), Q-decoder0_1, UART3 Data In (A).
13	PB2	bidirectional	High-voltage-resistant GPIO port B bit 2. Alt-functions: LP_Touch2, SPI4 Clock (A), Q-decoder0_0, ADC7, UART3 TXA, CAP5.
14	PB1	bidirectional	High-voltage-resistant GPIO port B bit 1. Hold LOW at power-up to reset the chip. Alt-functions: LP_Touch1, ADC6.
15	PB0	bidirectional	High-voltage-resistant GPIO port B bit 0. Alt-functions: LP_Touch0, TMR4 (Timer4 clock input).
16	BTRF	bidirectional	Bluetooth RF antenna interface (single-ended). Connect via matching network to the 2.4 GHz antenna. Supports BR/EDR/BLE up to +9 dBm TX and -95 dBm RX sensitivity.
17	VSS	power_in	System digital ground. Tie to the main ground plane.
18	XOSCI	input	System crystal oscillator input. Connect to one terminal of the external 24 MHz crystal with the standard load capacitors.
19	XOSCO	output	System crystal oscillator output (drive side). Connect to the other terminal of the 24 MHz crystal.
20	PC5	bidirectional	General purpose I/O port C bit 5. Alt-functions: SPI0_DAT2C, SD0_CLKA, SPI1 DOB, IIC0_SDA_B, ALNK_DAT3(B), ADC5, UART2 RXA.
21	PC4	bidirectional	General purpose I/O port C bit 4. Alt-functions: SPI0_DIC, SD0 CMDA, SPI1 CLKB, IIC0_SCL_B, ALNK_DAT2B, ADC4, UART2 TXA, PWM4.
22	PC3	bidirectional	General purpose I/O port C bit 3. Alt-functions: SPI0_CSC, SD0 DATOA, SPI1 DIB, ALNK_LRCKB, TMR3 (Timer3 clock input).
23	PC2	bidirectional	General purpose I/O port C bit 2. Alt-functions: SPI0_DOC, ALNK_SCLKB, TMR1 (Timer1 clock input).
24	USBDM	bidirectional	USB 2.0 full-speed D- data line (internal pull-down). Alt-functions: SDTAP_DATB, SPI2 DOB, IIC0_SDA_A, ADC11, UART1 RXB.
25	USBDP	bidirectional	USB 2.0 full-speed D+ data line (internal pull-down). Alt-functions: SDTAP_CLKB, SPI2 CLKB, IIC0_SCL_A, ADC10, UART1 TXB.
26	PA2	bidirectional	General purpose I/O port A bit 2. Alt-functions: MIC_BIAS0, MIC0_N, AMUX_A1, CLKOUT1, SPI1 CLKA, ALNK_MCLKA, UART1 RXA, CAP3.
27	PA1	bidirectional	General purpose I/O port A bit 1. Alt-functions: MICIN0, MIC0_P, AMUX_A0, SPI1 DIA, UART1 TXA, PWM0.
28	DACLP	output	Left channel audio DAC output (positive). 24-bit DAC with SNR ≥ 104 dB; can drive 16Ω/32Ω speakers directly in cap-less differential or single-ended mode.
29	DACRP	output	Right channel audio DAC output (positive). Matches DACLP for stereo output.
30	NC	unconnected	No connect. Datasheet marks type as 'P' but no function is documented; leave floating.
31	NC	unconnected	No connect. Datasheet marks type as 'P' but no function is documented; leave floating.
32	VCM	passive	Audio analog reference bias (common-mode) node. Requires an external decoupling capacitor to AVSS per JieLi reference design.
33	GND_PAD	power_in	Exposed thermal/ground pad (bottom of QFN-32). Datasheet lists this as PAD = VSS = System Ground. Must be soldered to the PCB ground plane for both electrical return and heat sinking.

Key specifications

Parameter	Value
Manufacturer	JieLi Tech
Package	QFN-32(4x4)
Category	Embedded Processors & Controllers
Pins	33

CAD (KiCad official)

Symbol: JL7016M8
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: JieLi Tech datasheet (19 pp, sha256 6260f48c4458fd3c, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF