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Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

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ISO3080DWR

Texas Instruments · RS-485 / RS-422 ICs · SOIC-16-300mil

ISO3080DWR from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC1	power_in	Logic-side supply voltage. 3.15-3.6 V for 3.3-V operation or 4.5-5.5 V for 5-V operation. Bypass to GND1 with a low-ESR ceramic capacitor close to the pin.
2	GND1	power_in	Logic-side (VCC1) ground reference. Isolated from the bus-side ground GND2 by the internal isolation barrier.
3	R	output	Receiver output on the logic side. Driven high when A-B > +200 mV, low when A-B < -200 mV, and held high by the fail-safe receiver when the bus is open, shorted, or idle. Referenced to VCC1/GND1.
4	RE	input	Receiver enable, active LOW. Drive low to enable the receiver output R; drive high to place R in high-impedance. 3.3-V compatible input that is also 5-V tolerant, VIH >= 2 V, VIL <= 0.8 V.
5	DE	input	Driver enable, active HIGH. Drive high to enable the differential driver outputs Y/Z; drive low to place them in high-impedance. 3.3-V compatible input, 5-V tolerant, VIH >= 2 V, VIL <= 0.8 V.
6	D	input	Driver data input on the logic side. Logic high produces Y high / Z low; logic low produces Y low / Z high (when DE is high). 3.3-V compatible, 5-V tolerant, VIH >= 2 V, VIL <= 0.8 V.
7	GND1	power_in	Logic-side ground. Tie to pin 2 GND1 externally. Multiple GND1 pins provide low-inductance return for the logic-side supply and improve isolation-barrier common-mode performance.
8	GND1	power_in	Logic-side ground. Tie to pin 2 GND1 externally. Multiple GND1 pins provide low-inductance return for the logic-side supply and improve isolation-barrier common-mode performance.
9	GND2	power_in	Bus-side ground. Tie to pin 10 and pin 15 GND2 externally. Isolated from GND1 by the internal barrier; provides the return for the RS-485 bus driver.
10	GND2	power_in	Bus-side ground. Tie to pin 9 and pin 15 GND2 externally. Isolated from GND1 by the internal barrier.
11	Y	output	Non-inverting differential driver output (RS-485 bus). Drives high when D=1 with DE=1, driving the far end high with respect to Z. VOD >= 1.5 V into 54 Ohm; VOC ~2.6 V typ. Withstands -7 V to +12 V bus common-mode range.
12	Z	output	Inverting differential driver output (RS-485 bus). Complementary to Y. Driver output current is limited (+/-60 mA) and the pin tolerates -9 V to +14 V absolute and -7 V to +12 V operating common-mode.
13	B	input	Inverting receiver differential input (RS-485 bus). Together with A senses the received differential signal; receiver output R goes low when A-B < -200 mV. Presents 1/8 unit load (>=96 kOhm), allowing up to 256 nodes on one bus.
14	A	input	Non-inverting receiver differential input (RS-485 bus). Receiver output R goes high when A-B > +200 mV; fail-safe biasing forces R high when the bus is open, shorted, or idle. -7 V to +12 V common-mode.
15	GND2	power_in	Bus-side ground. Tie to pins 9 and 10 GND2 externally. Provides the return for VCC2 and the RS-485 bus driver.
16	VCC2	power_in	Bus-side supply voltage, 4.5-5.5 V. Powers the isolated RS-485 driver/receiver. Bypass to GND2 with a low-ESR ceramic capacitor close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16-300mil
Category	Interface
Pins	16

Ordering variants

ISO3080DWR
ISO3080DWRDWG4
ISO3080DWRG4

CAD (KiCad official)

Symbol: ISO3080DWR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16-300mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (None pp, sha256 7c74bf82e645e79f, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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