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isl6752aaza-t
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RENESAS DC-DC Converters, QSOP-16-150mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.
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RENESAS · DC-DC Converters · QSOP-16-150mil
ISL6752AAZA-T from RENESAS, in a QSOP-16-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VADJ | input | 0 V to 5.0 V control input that sets the phase relationship between the SR outputs (OUTLLN/OUTLRN) and the lower PWM outputs (OUTLL/OUTLR). VADJ < 2.425 V advances the SR outputs; VADJ > 2.575 V delays them; 2.50 V ±75 mV gives zero phase difference. A weak internal 50% divider from VREF holds the pin at ~2.5 V when left open. |
| 2 | VREF | power_out | 5.0 V ±3% precision reference output over line, load and temperature. Sources up to 10 mA and sinks at least 5 mA; short-circuit current limited to -15 mA to -100 mA. Bypass to GND with a 0.1 µF to 2.2 µF low-ESR capacitor. |
| 3 | VERR | input | Inverting input of the PWM comparator; accepts the external error-amplifier signal directly or via an opto-coupler for closed-loop regulation. Internally pulled up by a nominal 1 mA current source; VOH is at least 4.20 V open circuit. Zero-duty-cycle occurs when VERR < ~0.85-1.20 V. |
| 4 | CTBUF | output | Buffered replica of the CT sawtooth oscillator waveform, capable of sourcing 2 mA. Nominal valley-to-peak gain of 2 V/V with a 0.40 V offset above GND. Suitable for slope compensation. |
| 5 | RTD | input | Oscillator timing-capacitor discharge current programming pin; nominal 2.0 V. The current in a resistor from RTD to GND sets the CT discharge current (nominally 20× the resistor current), which determines the PWM dead time. Maximum recommended RTD current is 1 mA (20 mA CT discharge). |
| 6 | RESDEL | input | Sets the resonant delay between the toggle of the upper FETs and the turn-on of a lower FET. Applied voltage 0 V to 2 V scales resonant delay from 0 % to 100 % of the dead time (V/2 = fraction of dead time); operate below 2 V so the lower FETs are OFF before the uppers switch. |
| 7 | CS | input | Overcurrent-comparator input; nominal 1.00 V threshold with 70 ns leading-edge blanking and ~35 ns CS-to-OUT delay (excluding LEB). Internally shorted to GND (≤20 Ω) at the termination of each PWM output. Input bias current is -2 µA to -6 µA at VCS = 0.3 V; a series input resistor may be required with high-impedance sense sources. |
| 8 | CT | passive | Oscillator timing capacitor node. CT is charged from GND by an internal 200 µA source (valley 0.80 V, peak 2.80 V, 2.0 Vp-p) and discharged by a user-adjustable current set through RTD. |
| 9 | OUTLL | output | Lower-left bridge FET gate drive. Pulse-width-modulated, operates in alternate sequence with OUTLR. Peak gate current 0.1 A (per absolute max), rise/fall ~110/90 ns into 220 pF at VDD = 15 V; clamped to ≤1.25 V during UVLO. |
| 10 | GND | power_in | Signal and power ground return for the device. A low-impedance layout with ground planes and short traces is required because of high peak gate currents and high-frequency operation. |
| 11 | OUTLRN | output | Complement of the lower-right PWM output OUTLR, suitable for driving synchronous rectifiers. Phase relative to OUTLR is controlled by VADJ (advance for VADJ < 2.425 V, delay for VADJ > 2.575 V, up to ±40 ns to ±300 ns). |
| 12 | OUTLLN | output | Complement of the lower-left PWM output OUTLL, suitable for driving synchronous rectifiers. Phase relative to OUTLL is controlled by VADJ (see VADJ description). |
| 13 | OUTUR | output | Upper-right bridge FET gate drive. Operates at fixed 50% duty cycle in alternate sequence with OUTUL. Peak gate current 0.1 A; UVLO output clamp ≤1.25 V. |
| 14 | OUTUL | output | Upper-left bridge FET gate drive. Operates at fixed 50% duty cycle in alternate sequence with OUTUR. Peak gate current 0.1 A; UVLO output clamp ≤1.25 V. |
| 15 | OUTLR | output | Lower-right bridge FET gate drive. Pulse-width-modulated, operates in alternate sequence with OUTLL. Peak gate current 0.1 A, rise/fall ~110/90 ns into 220 pF at VDD = 15 V; clamped to ≤1.25 V during UVLO. |
| 16 | VDD | power_in | Bias supply, recommended 9 V to 16 V (absolute max 20 V). Monitored by UVLO (typ 8.75 V start / 7.00 V stop, 1.75 V hysteresis). Start-up current 175 µA typ, operating current 11 mA typ. Bypass to GND with a ceramic capacitor as close to VDD/GND as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | QSOP-16-150mil |
| Category | PMIC |
| Pins | 16 |
Ordering variants
ISL6752AAZA-T
CAD (KiCad official)
- Symbol:
ISL6752AAZA-T - Footprint:
Package_SO:QSOP-16_3.9x4.9mm_P0.635mm - 3D model: QSOP-16-150mil (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (None pp, sha256
3e5ee7fd5b5148da, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).