IS25LP040E-JYLA3-TR from ISSI Integrated Silicon Solution, in a USON-8-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CE#	input	Chip Enable, active low. When high the device is deselected and enters low-power standby with high-impedance outputs. Must transition from high to low after power-up before a new instruction is accepted.
2	SO/IO1	bidirectional	Serial Data Output in standard SPI mode (unidirectional, data driven on falling edge of SCK). In Dual/Quad SPI and QPI modes it becomes bidirectional IO1.
3	WP#/IO2	bidirectional	Write Protect input (active low) in standard SPI: protects Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) from being written when SRWD=1. When QE=1 or in Quad/QPI modes the pin serves as bidirectional IO2 and the WP# function is unavailable.
4	GND	power_in	Device ground. Connect to system ground reference for Vcc.
5	SI/IO0	bidirectional	Serial Data Input in standard SPI mode (unidirectional, latched on rising edge of SCK for instructions, addresses, and write data). In Dual/Quad SPI and QPI modes it becomes bidirectional IO0.
6	SCK	input	Serial Clock input. Synchronizes all input and output timing. Supports SPI modes (0,0) and (1,1) up to 104MHz fast-read (416MHz equivalent throughput in QPI).
7	HOLD#/IO3	bidirectional	Hold input (active low) in standard SPI: pauses serial communication without resetting the sequence while CE# is low; SO is high-Z while HOLD# is low. When QE=1 (Quad enabled) or in QPI mode, the pin becomes bidirectional IO3 and HOLD# function is unavailable.
8	VCC	power_in	Core power supply. IS25LP variant range 2.30V to 3.60V (IS25WP variant would be 1.70V to 1.95V). Decouple to GND per manufacturer recommendation.

Key specifications

Parameter	Value
Manufacturer	ISSI Integrated Silicon Solution
Package	USON-8-EP(2x3)
Category	Memory
Pins	8

Ordering variants

Same part, different packaging or reel option.

IS25LP040E-JYLA3-TRB
IS25LP040E-JYLA3-TRN
IS25LP040E-JYLA3-TRV
IS25LP040E-JYLA3-TRY
IS25LP040E-JYLA3-TRD
IS25LP040E-JYLA3-TRK

CAD (KiCad official)

Symbol: IS25LP040E-JYLA3-TR
Footprint: Package_SON:Winbond_USON-8-1EP_3x2mm_P0.5mm_EP0.2x1.6mm
3D model: USON-8-EP(2x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ISSI Integrated Silicon Solution datasheet (93 pp, sha256 682d1cb75600d9cd, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF