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is25lp032d-jnle-tr
Public Unreviewedby Ray
ISSI Integrated Silicon Solution NOR FLASH, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownIS25LP032D-JNLE-TR
ISSI Integrated Silicon Solution · NOR FLASH · SOIC-8
IS25LP032D-JNLE-TR from ISSI Integrated Silicon Solution, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip Enable (active-low). Drive low to select the device and bring it out of standby; drive high to deselect and place outputs in high-Z / standby (typ. 10 µA). After power-up, CE# must transition high-to-low before any new instruction is accepted. |
| 2 | SO/IO1 | bidirectional | Serial Data Output in Standard SPI (data/status clocked out on SCK falling edge). In Dual/Quad/QPI modes this pin becomes bidirectional IO1 for both instruction/address input and data output. Compatible with SPI modes 0 and 3. |
| 3 | WP#/IO2 | bidirectional | Write Protect (active-low) in Standard/Dual SPI: when SRWD=1 and WP# is low, the Status Register bits SRWD/QE/BP3-BP0 are hardware write-protected. In Quad SPI / QPI (QE=1) this pin becomes bidirectional data line IO2 and the WP# function is unavailable. |
| 4 | GND | power_in | Device ground reference. Return for Vcc. |
| 5 | SI/IO0 | bidirectional | Serial Data Input in Standard SPI (instructions/addresses/data clocked in on SCK rising edge). In Dual/Quad/QPI modes this pin becomes bidirectional IO0 for both input and output. Compatible with SPI modes 0 and 3. |
| 6 | SCK | input | Serial Clock input for all SPI/QPI transfers (up to 133 MHz STR, 66 MHz DTR). Provides the synchronized reference clock for both input and output timing. |
| 7 | HOLD#/RESET#/IO3 | bidirectional | Multi-function pin. With QE=0 it acts as HOLD# (P7=0, default) or RESET# (P7=1) selected by the P7 bit of the Read Register. HOLD# pauses serial activity while CE# is low, placing SO in high-Z; RESET# forces the device into reset when driven low. When QE=1 (Quad/QPI mode) it becomes bidirectional data line IO3. |
| 8 | Vcc | power_in | Device core power supply. IS25LP032D: 2.30 V to 3.60 V (IS25WP variant: 1.65 V to 1.95 V). Typical active read current 4 mA; standby 10 µA; deep power-down 1 µA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ISSI Integrated Silicon Solution |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
IS25LP032D-JNLE-TRIS25LP032D-JNLE-TRQNLEIS25LP032D-JNLE-TRJNLA3IS25LP032D-JNLE-TRQNLA3IS25LP032D-JNLE-TRJBLEIS25LP032D-JNLE-TRQBLEIS25LP032D-JNLE-TRJBLA3IS25LP032D-JNLE-TRQBLA3IS25LP032D-JNLE-TRJTLEIS25LP032D-JNLE-TRJTLA3IS25LP032D-JNLE-TRQTLA3IS25LP032D-JNLE-TRJELEIS25LP032D-JNLE-TRJELA3IS25LP032D-JNLE-TRJKLEIS25LP032D-JNLE-TRJKLA3IS25LP032D-JNLE-TRJLLA3IS25LP032D-JNLE-TRRMLEIS25LP032D-JNLE-TRRMLA3IS25LP032D-JNLE-TRRGLEIS25LP032D-JNLE-TRRGLA3IS25LP032D-JNLE-TRRHLEIS25LP032D-JNLE-TRRHLA3
CAD (KiCad official)
- Symbol:
IS25LP032D-JNLE-TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ISSI Integrated Silicon Solution datasheet (None pp, sha256
2777d8e9f25bc2c3, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).