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Contents

README

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IPD040N03L G

Infineon Technologies · MOSFETs · TO-252

IPD040N03L G from Infineon Technologies, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate. Isolated MOS control terminal; drives the channel via V_GS relative to source. V_GS(th) = 1 V (min) to 2.2 V (max) at V_DS=V_GS, I_D=250 µA. Absolute-max V_GS = ±20 V. Total gate charge Q_g ≈ 18 nC (typ) at V_GS=0→10 V, V_DD=15 V, I_D=30 A.
2 D passive Drain (also the tab on PG-TO252-3-11). Power terminal; sinks channel current from load to source when the FET is enhanced. V_(BR)DSS ≥ 30 V, R_DS(on) typ 3.3 mΩ / max 4 mΩ at V_GS=10 V, I_D=30 A. Continuous I_D up to 90 A at V_GS=10 V, T_C=25 °C; pulsed I_D,pulse up to 400 A. Tab is electrically the drain.
3 S passive Source. Reference terminal for the gate drive and the anode of the intrinsic body diode. Diode continuous forward current I_S = 66 A, V_SD ≈ 0.83 V typ / 1.1 V max at V_GS=0, I_F=30 A, T_j=25 °C; reverse recovery charge Q_rr ≈ 20 nC.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TO-252
Category Transistors/Thyristors
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • IPD040N03L G
  • IPD040N03L GIPS040N03L G

CAD (KiCad official)

  • Symbol: IPD040N03L G
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (10 pp, sha256 14bc5fa40814ef10, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF