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icw5176qder
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ICW DC-DC Converters, QFN-32(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownICW5176QDER
ICW · DC-DC Converters · QFN-32(4x4)
ICW5176QDER from ICW, in a QFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | /CE | input | Chip Logic Enable, active low (CE=Low enables chip). Contains an internal pull-down resistor so the chip defaults to enabled when floating. |
| 2 | NC | unconnected | No connection. Leave floating. |
| 3 | PWM | input | PWM input, accepts 20kHz-100kHz square wave. Duty cycle sets VOUT: duty=0% → VOUT = 1/6 of FB-preset value; duty=100% → VOUT = FB-preset value. Internal pull-down keeps VOUT at 1/6 when floating. |
| 4 | PG | output | Power Good indicator. Open-drain, active high when VOUT is within 90% to 110% of target. Requires external pull-up. Leave floating if not used. |
| 5 | IPWM | input | PWM input (20kHz-100kHz) used with ITUNE to dynamically adjust current limit ILIM1 (input) or ILIM2 (output). Current limit is proportional to duty cycle: ILIMx = ILIMx_SET × D. |
| 6 | ITUNE | bidirectional | Selects which current limit (ILIM1 or ILIM2) the IPWM signal controls. The chosen ILIMx resistor is connected between the ILIMx pin and ITUNE pin. Only one current limit can be selected. Leave floating if IPWM/ITUNE function is not used. |
| 7 | NC | unconnected | No connection. Leave floating. |
| 8 | DT | input | Dead-time selection via resistor to GND. Short to GND: 20ns; 68kΩ (±10%): 40ns; 270kΩ (±10%): 60ns; Open: 80ns. New setting applied on next power-up (not real-time). |
| 9 | NC | unconnected | No connection. Leave floating. |
| 10 | FREQ | input | Switching frequency selection via resistor to GND. Short to GND: 200kHz; 68kΩ (±10%): 400kHz; Open: 600kHz. Not real-time - applied on next power-up. |
| 11 | ILIM1 | input | Input current limit programming pin. Connect resistor RLIM1 to AGND (or to ITUNE for real-time control). ILIM1 = VREF × RLIM1 / (RSNS1 × RSS1) using VREF=1.21V, typical RSS1=1kΩ, RSNS1=5-10mΩ. Add 2.2nF (or 10nF if IPWM used) filter capacitor. Short to GND to disable input current limit. |
| 12 | ILIM2 | input | Output current limit programming pin. Connect resistor RLIM2 to AGND (or to ITUNE for real-time control). ILIM2 = VREF × RLIM2 / (RSNS2 × RSS2) using VREF=1.21V, typical RSS2=1kΩ, RSNS2=5-10mΩ. Add 2.2nF (or 10nF if IPWM used) filter capacitor. Short to GND to disable output current limit. |
| 13 | NC | unconnected | No connection. Leave floating. |
| 14 | AGND | power_in | Analog ground reference for internal control circuitry. Connect to system ground plane; the thermal pad may also be tied to AGND. |
| 15 | COMP | output | Feedback loop compensation node. Connect external RC network (typically 4.99kΩ + 47nF to AGND) to set loop response. Increase resistor value (e.g. 10-20kΩ) for faster response. |
| 16 | FB | input | Output voltage feedback input. Connect resistor divider from VOUT to AGND. VOUT_SET = VFB_REF × (1 + RUP/RDOWN), with internal VFB_REF ≈ 1.22V. |
| 17 | SNS2N | input | Negative input of the output-side current sense amplifier. Connect through RSS2 (~1kΩ) to the VOUT-side of external sense resistor RSNS2. Current flows from SNS2P to SNS2N. |
| 18 | SNS2P | input | Positive input of the output-side current sense amplifier. Connect through RSS2 (~1kΩ) to the MOSFET-side of external sense resistor RSNS2. Current flows from SNS2P to SNS2N. |
| 19 | VOUT | power_in | Output node sense of the buck-boost converter. Absolute max 42V. Also used internally as a candidate source for VCC bias regulator. |
| 20 | BT2 | power_in | Bootstrap capacitor node for high-side driver 2. Connect a bootstrap capacitor between BT2 and SW2 to generate the floating bias supply for HD2. Absolute max 50V; BT2-to-SW2 ≤ 12V. |
| 21 | HD2 | output | High-side MOSFET gate driver output for the output-side leg (Q4). Referenced to SW2. Typical pull-up ≈ 1.5Ω, pull-down ≈ 1Ω. Add optional series gate resistor (0603) between HD2 and MOSFET gate for EMI tuning. |
| 22 | SW2 | power_in | Switching node 2 (output-side half-bridge). Connect to the source of Q4/drain of Q3 and to the bootstrap capacitor return for BT2. Absolute max range -1V to 42V. |
| 23 | LD2 | output | Low-side MOSFET gate driver output for the output-side leg (Q3). Referenced to PGND, driven from VCC (10V). Typical pull-up ≈ 1.5Ω, pull-down ≈ 1Ω. |
| 24 | VCC | power_out | Internal LDO regulator output providing ~10V bias to the gate drivers. Sourced from the higher of VIN/VOUT and clamped to ~10V. Bypass with a 1µF ceramic capacitor to PGND. Current limit 75-100mA. |
| 25 | PGND | power_in | Power ground return for gate drivers and VCC bypass. Connect to system ground plane; thermal pad may also be tied to PGND. |
| 26 | LD1 | output | Low-side MOSFET gate driver output for the input-side leg (Q2). Referenced to PGND, driven from VCC (10V). Typical pull-up ≈ 1.5Ω, pull-down ≈ 1Ω. |
| 27 | SW1 | power_in | Switching node 1 (input-side half-bridge). Connect to the source of Q1/drain of Q2 and to the bootstrap capacitor return for BT1. Absolute max range -1V to 42V. |
| 28 | HD1 | output | High-side MOSFET gate driver output for the input-side leg (Q1). Referenced to SW1. Typical pull-up ≈ 1.5Ω, pull-down ≈ 1Ω. Optional series gate resistor (0603) for EMI tuning. |
| 29 | BT1 | power_in | Bootstrap capacitor node for high-side driver 1. Connect a bootstrap capacitor between BT1 and SW1 to generate the floating bias supply for HD1. Absolute max 50V; BT1-to-SW1 ≤ 12V. |
| 30 | VIN | power_in | Input voltage sense/supply pin of the buck-boost converter. Operating range 2.7V to 36V (absolute max 42V). Also used internally as candidate source for VCC bias regulator. |
| 31 | SNS1N | input | Negative input of the input-side current sense amplifier. Connect through RSS1 (~1kΩ) to the VIN-side of external sense resistor RSNS1. Current flows from SNS1P to SNS1N. |
| 32 | SNS1P | input | Positive input of the input-side current sense amplifier. Connect through RSS1 (~1kΩ) to the MOSFET-side of external sense resistor RSNS1. Current flows from SNS1P to SNS1N. |
| 33 | EP | power_in | Exposed thermal pad on package bottom. Connect to AGND or PGND for thermal dissipation and low-impedance ground return. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ICW |
| Package | QFN-32(4x4) |
| Category | PMIC |
| Pins | 33 |
Ordering variants
ICW5176QDER
CAD (KiCad official)
- Symbol:
ICW5176QDER - Footprint:
Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm - 3D model: QFN-32(4x4) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ICW datasheet (None pp, sha256
de51fe04b3a71bb5, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).