HR8825 from Jiaxing Heroic Elec Tech, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CP1	passive	Charge pump flying capacitor terminal 1. Connect a 0.1uF capacitor between CP1 and CP2 to build the high-side gate drive charge pump.
2	CP2	passive	Charge pump flying capacitor terminal 2. Pairs with CP1 via a 0.1uF capacitor for internal charge pump generation.
3	VCP	power_out	Charge pump reservoir / high-side gate drive supply. Connect a 0.1uF capacitor from VCP to VM.
4	VMA	power_in	A-bridge motor supply, 8V to 32V. All VM pins must be tied together and bypassed to GND (≥100uF bulk plus 0.1uF ceramic close to pin).
5	AOUT1	output	A-bridge H-bridge output 1. Connects to one terminal of the stepper motor A-phase coil. Rated ±2.5A (positive current is defined as AOUT1 → AOUT2).
6	ISENA	passive	A-bridge current-sense return. Connect the A-bridge sense resistor Rs from ISENA to GND; VTRIP is regulated to VAVREF/5.
7	AOUT2	output	A-bridge H-bridge output 2. Connects to the other terminal of the stepper motor A-phase coil.
8	BOUT2	output	B-bridge H-bridge output 2. Connects to one terminal of the stepper motor B-phase coil. Positive current direction is BOUT1 → BOUT2.
9	ISENB	passive	B-bridge current-sense return. Connect the B-bridge sense resistor Rs from ISENB to GND.
10	BOUT1	output	B-bridge H-bridge output 1. Connects to the other terminal of the stepper motor B-phase coil.
11	VMB	power_in	B-bridge motor supply, 8V to 32V. Must be tied to VMA - all VM pins connect to the same supply.
12	AVREF	input	A-bridge current-set reference input, 1V to 3.5V (VREF absolute max -0.3 to 4V). Chopping current ICHOP = VAVREF / (5·Rs). Typically tied to BVREF and to V3P3OUT via a divider with 0.1uF bypass.
13	BVREF	input	B-bridge current-set reference input, 1V to 3.5V. Usually tied to AVREF so both bridges share the same reference.
14	GND	power_in	Device ground. All GND pins and the exposed thermal pad must be tied to the PCB ground plane.
15	V3P3OUT	power_out	Internal 3.3V LDO output (3.1V min / 3.5V max, up to 1mA load). Bypass with 0.1uF to GND; may be used to bias VREF and pull-ups.
16	nRESET	input	Active-low reset input. Low resets internal logic and sets the microstep indexer to HOME while disabling H-bridges; STEP inputs are ignored. Internal 100kΩ pull-down.
17	nSLEEP	input	Active-low sleep input. Low enters low-power sleep (H-bridges, charge pump and V3P3OUT disabled). On rising edge wait tWAKE ≈ 1ms before applying STEP. Internal 100kΩ pull-down.
18	nFAULT	output	Open-drain fault output. Pulled low on overcurrent (OCP) or thermal shutdown (TSD). Requires external pull-up (e.g. 10kΩ to V3P3OUT). VOL = 0.35V typ at 5mA.
19	DECAY	input	Decay-mode select. Tied low = slow-rise mixed-decay fall (~25us); left floating or high = full mixed decay. External pull-down resistor (22k-100k) trims decay time. Internal 22kΩ pull-down.
20	DIR	input	Direction control input. Sets the direction advanced by the internal microstep indexer on each STEP rising edge. Internal 100kΩ pull-down.
21	nENBL	input	Active-low output enable. Low enables the H-bridge outputs; high tri-states the outputs while the indexer continues to track STEP. Internal 100kΩ pull-down.
22	STEP	input	Step clock input. Rising edge advances the microstep indexer by one step. fSTEP up to 250kHz; tWH/tWL ≥ 1.9us. Internal 100kΩ pull-down.
23	NC	unconnected	No connect. Leave floating (no defined function).
24	MODE0	input	Microstep resolution select bit 0. MODE[2:0] selects full/1/2/1/4/1/8/1/16/1/32-step operation per Table 1. Internal 100kΩ pull-down.
25	MODE1	input	Microstep resolution select bit 1. See MODE0. Internal 100kΩ pull-down.
26	MODE2	input	Microstep resolution select bit 2 (MSB). See MODE0. Internal 100kΩ pull-down.
27	nHOME	output	Open-drain HOME status output. Asserted low when the internal microstep indexer is at HOME position. Requires external pull-up.
28	GND	power_in	Device ground (second GND pin). Must be tied together with pin 14 GND and the exposed thermal pad (PPAD).
PPAD	GND	power_in	Exposed thermal pad on the underside of the ETSSOP-28 package. Must be soldered to the ground plane for both electrical and thermal performance.

Key specifications

Parameter	Value
Manufacturer	Jiaxing Heroic Elec Tech
Package	HTSSOP-28-EP
Category	Motor Driver ICs
Pins	29

Ordering variants

Same part, different packaging or reel option.

HR8825MTER
HR8825MTERA

CAD (KiCad official)

Symbol: HR8825
Footprint: Package_SO:HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP3.4x9.5mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Jiaxing Heroic Elec Tech datasheet (19 pp, sha256 91d3f5799f038978, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF