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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

HR1001CGS-Z

Monolithic Power Systems · AC-DC Controllers And Regulators · SOIC-16

HR1001CGS-Z from Monolithic Power Systems, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SS	passive	Soft start. Connect an external capacitor from SS to GND and a resistor to FSET to program the maximum oscillator frequency and the frequency-shift time constant during start-up. An internal switch discharges this capacitor when the chip turns off (VCC < UVLO, BO fault, LATCH tripped, CS > VCS-OCP, TIMER > VTIMER-fmax, or thermal shutdown) to guarantee a soft start on the next cycle.
2	TIMER	passive	Over-current-to-shutdown period. A capacitor and resistor from TIMER to GND set the maximum duration allowed in over-current before the IC stops switching and the delay before it resumes. An internal current source ITIMER charges the capacitor whenever VCS > VCS-OCR; the external resistor discharges it slowly. Reaching VTIMER-fmax forces the SS cap to fully discharge (freq → max); exceeding VTIMER-SD halts switching until the voltage decays below VTIMER-R, when the IC re-enters soft start.
3	CT	passive	Oscillator timing capacitor. An internal current source (programmed by the network on FSET) alternately charges and discharges a capacitor tied from CT to GND between VCFp and VCFv thresholds, setting the converter's switching frequency.
4	FSET	passive	Switching frequency set / precise 2 V reference. A resistor from FSET to GND defines the current that sets the minimum oscillator frequency. Tying the optocoupler phototransistor to FSET through a resistor closes the feedback loop that modulates the oscillator and regulates the output; that resistor's value sets the maximum operating frequency. An R-C series from FSET to GND sets the start-up frequency shift to limit inrush energy. Source current rating 2 mA max.
5	BURST	input	Burst-mode threshold. BURST senses the feedback-related voltage and is compared to an internal VBurst reference. Below VBurst the IC enters an idle low-Iq state; when feedback drives BURST above VBurst + 30 mV (VBurst-hys) switching resumes with no soft start. This enables light-load burst operation whose entry point is set by a resistor from the optocoupler to FSET. Tie BURST to FSET if burst mode is not used.
6	CS	input	Half-bridge current sense (also used for CMP). Sensed via a resistor or capacitive divider on the primary. Three functions: (1) over-current regulation - VCS > VCS-OCR discharges SS and pushes frequency up; (2) over-current protection - VCS > VCS-OCP with VSS < VSS-OCP latches OCP off (cleared by cycling VCC below UVLO); (3) capacitive-mode protection - CS is compared to VCSNR/VCSPR after each gate turn-off to block the opposite gate until the correct dV/dt slope is detected or the CMP timer expires. Absolute rating −3 V to +6 V. Tie CS to GND if CMP is not used.
7	BO	input	Input voltage sense and brown-in/brown-out protection. When BO rises above VBO-On the IC enables the gate drivers; when BO falls below VBO-Off the IC is disabled. Also supports remote on/off.
8	LATCH	input	IC latched shutdown input. When VLATCH is exceeded the IC shuts down and drops its bias current near the pre-start-up level. Reset only when VCC is discharged below its UVLO threshold. Connect LATCH to GND if not used.
9	HBVS	input	Half-bridge dV/dt sense for adaptive dead-time. A high-voltage capacitor is tied between SW and HBVS; the dV/dt current through HBVS is measured to adaptively adjust the dead time between HG and LG. Sink current ±65 mA max.
10	GND	power_in	Ground. Return for the low-side gate driver and the IC bias. Route separate traces from GND to the signal ground and to the pulsed gate-current return.
11	LG	output	Low-side gate driver output. Push-pull driver with ±0.8 A peak source/sink to drive the low-side half-bridge MOSFET. Held at GND during UVLO. Voltage rating −0.3 V to VCC.
12	VCC	power_in	Supply voltage for the IC bias and the low-side gate driver. Recommended operating range 13 V to 15.5 V (self-limited internally). Decouple with a small (e.g. 0.1 µF) bypass capacitor at the pin.
13	NC	unconnected	High-voltage spacer. No internal connection. Provided to isolate the high-voltage SW pin from the low-voltage side and to ease safety-agency creepage-distance compliance on the PCB.
14	SW	power_in	High-side driver source / half-bridge switching node return. Current return for the high-side gate drive. Requires careful layout to avoid large negative spikes below GND. Rated −3 V to +600 V with a maximum dV/dt of 50 V/ns.
15	HG	output	High-side floating gate driver output. Push-pull driver with ±0.8 A peak source/sink to drive the upper half-bridge MOSFET, referenced to SW. An internal pull-down resistor to SW prevents HG from floating during UVLO.
16	BST	power_in	Bootstrap supply for the floating high-side gate driver. Connect a bootstrap capacitor between BST and SW; it is charged by an internal bootstrap diode driven in phase with the low-side gate driver. Absolute rating −0.3 V to +618 V.

Key specifications

Parameter	Value
Manufacturer	Monolithic Power Systems
Package	SOIC-16
Category	Power Management (PMIC)
Pins	16

Ordering variants

Same part, different packaging or reel option.

HR1001CGS-Z

CAD (KiCad official)

Symbol: HR1001CGS-Z
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Monolithic Power Systems datasheet (None pp, sha256 05a190f3b063515a, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF