component
hg9200bm
Public Unreviewedby Ray
HGSEMI Audio Interface ICs, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownHG9200BM
HGSEMI · Audio Interface ICs · SOP-14
HG9200BM from HGSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE | input | Chip enable, active low. CMOS input with internal pull-high. Drive low to enable oscillator and DTMF output; drive high to place the device in standby (I_STB ≤ 2 µA at 5 V). |
| 2 | X2 | output | Oscillator output. Along with X1 forms the inverter/bias-resistor oscillator with on-chip load capacitors. Connect a standard 3.579545 MHz crystal between X1 and X2. |
| 3 | X1 | input | Oscillator input. Connect a standard 3.579545 MHz crystal or ceramic resonator between X1 and X2. Internal bias resistor (~10 MΩ) and load caps (~20 pF/10 pF) are integrated. |
| 4 | VSS | power_in | Negative supply / ground reference. |
| 5 | NC | unconnected | No internal connection. Leave floating or tie to ground per board convention. |
| 6 | D0 | input | Parallel-mode data input bit 0 (LSB of the 4-bit digit code in Table 2). In serial mode this pin is pulled high internally and should be left floating; in parallel mode it must not be floated. |
| 7 | D1 | input | Parallel-mode data input bit 1. Pull-high internal resistor when in serial mode; drive as parallel data input when S/P=H. |
| 8 | D2 | input | Parallel-mode data input bit 2. Pull-high internal resistor when in serial mode; drive as parallel data input when S/P=H. |
| 9 | D3 | input | Parallel-mode data input bit 3 (MSB of the 4-bit parallel code). Pull-high internal resistor when in serial mode; drive as parallel data input when S/P=H. |
| 10 | S/P | input | Operation-mode select. CMOS input: S/P = H selects parallel mode (D0-D3 drive the tone code); S/P = L selects serial mode (DATA/CLK stream a 5-bit code). |
| 11 | CLK | input | Serial-mode synchronous clock input. In parallel mode this pin is pulled high internally and can be left floating; in serial mode it clocks in 5-bit codes on the falling edge (100 kHz typ, 500 kHz max). |
| 12 | DATA | input | Serial-mode data input. In parallel mode this pin is pulled high internally and can be left floating; in serial mode it is latched on the falling edge of CLK, D0 (LSB) first. |
| 13 | DTMF | output | DTMF analog output. CMOS output providing the selected single/dual tone (V_TAC ≈ 0.15 Vrms into R_L=5 kΩ, DC level ≈ 0.45-0.75 × VDD). Requires R_L ≥ 5 kΩ. |
| 14 | VDD | power_in | Positive supply, 2.0-5.5 V for normal operation. I_DD ≈ 240 µA at 2.5 V and 950 µA at 5.0 V with CE=VSS and no load. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-14 |
| Category | Interface |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
HG9200BM/TRHG9200BMANHG9200BMAM/TR
CAD (KiCad official)
- Symbol:
HG9200BM - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (12 pp, sha256
e155baa26afbb02c, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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