component
HEF4070BT
Public Unreviewedby Ray
Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownHEF4070BT
Nexperia · Gates · SOIC-14
HEF4070BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 data input A. CMOS logic input with clamp diodes; recommended input voltage range 0 V to VDD (3-15 V). |
| 2 | 1B | input | Gate 1 data input B. CMOS logic input with clamp diodes; recommended input voltage range 0 V to VDD (3-15 V). |
| 3 | 1Y | output | Gate 1 data output. XOR of 1A and 1B; rail-to-rail CMOS output (VOH >= VDD - 0.05 V, VOL <= 0.05 V at |
| 4 | 2Y | output | Gate 2 data output. XOR of 2A and 2B; rail-to-rail CMOS output. |
| 5 | 2A | input | Gate 2 data input A. CMOS logic input with clamp diodes. |
| 6 | 2B | input | Gate 2 data input B. CMOS logic input with clamp diodes. |
| 7 | VSS | power_in | Ground reference (0 V) for the device. |
| 8 | 3A | input | Gate 3 data input A. CMOS logic input with clamp diodes. |
| 9 | 3B | input | Gate 3 data input B. CMOS logic input with clamp diodes. |
| 10 | 3Y | output | Gate 3 data output. XOR of 3A and 3B; rail-to-rail CMOS output. |
| 11 | 4Y | output | Gate 4 data output. XOR of 4A and 4B; rail-to-rail CMOS output. |
| 12 | 4A | input | Gate 4 data input A. CMOS logic input with clamp diodes. |
| 13 | 4B | input | Gate 4 data input B. CMOS logic input with clamp diodes. |
| 14 | VDD | power_in | Positive supply voltage. Recommended operating range 3 V to 15 V; absolute maximum -0.5 V to +18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
HEF4070BTT
CAD (KiCad official)
- Symbol:
HEF4070BT - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
hef4070bt.step |
195 KB | You want the bare part, or you mark your own boards. |
hef4070bt-etched.step |
2.0 MB | You want the part with HEF4070BT already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 519 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (9 pp, sha256
40c2fad27ae2a3fd, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).